kernel/linux.git/drivers/pinctrl/qcom/Kconfig, branch v6.3.2

pinctrl: qcom: Introduce IPQ5332 TLMM driver

2023-02-07T14:44:39+00:00

The IPQ5332 SoC comes with a TLMM block, like all other Qualcomm platforms, so add a driver for it. Signed-off-by: Kathiravan T Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20230206071217.29313-3-quic_kathirav@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS

2023-02-06T11:15:51+00:00

Add druver for pin controller in Low Power Audio SubSystem (LPASS). The driver is similar to SM8450 LPASS pin controller, with differences in few pin groups (qua_mi2s -> i2s0). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230203174645.597053-2-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: add the tlmm driver sa8775p platforms

2023-02-01T22:44:49+00:00

Add support for Lemans TLMM configuration and control via the pinctrl framework. Signed-off-by: Yadu MG Signed-off-by: Prasad Sodagudi [Bartosz: made the driver ready for upstream] Co-developed-by: Bartosz Golaszewski Signed-off-by: Bartosz Golaszewski Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20230201150011.200613-3-brgl@bgdev.pl Signed-off-by: Linus Walleij

pinctrl: qcom: Add SM8550 pinctrl driver

2023-01-09T13:20:52+00:00

Add pinctrl driver for TLMM block found in SM8550 SoC. Co-developed-by: Neil Armstrong Signed-off-by: Neil Armstrong Signed-off-by: Abel Vesa Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221230203637.2539900-3-abel.vesa@linaro.org Reviewed-by: Bjorn Andersson Signed-off-by: Linus Walleij

pinctrl: qcom: Add QDU1000/QRU1000 pinctrl driver

2022-12-29T01:34:53+00:00

Add pin control driver for the TLMM block found in the QDU1000 and QRU1000 SoC. Signed-off-by: Melody Olvera Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20221216230852.21691-3-quic_molvera@quicinc.com Signed-off-by: Linus Walleij

pinctrl: qcom: add sdm670 pinctrl

2022-10-17T09:27:28+00:00

The Snapdragon 670 has a Top-Level Mode Multiplexer (TLMM) for various features. Add a driver to support it. Link: https://android.googlesource.com/kernel/msm/+/de5a12173c7fa6d65bedee9ad36af55b2dbfeb36%5E%21/#F6 Link: https://android.googlesource.com/kernel/msm/+/04f083156d9b9f3bfcf204c1c6da88632fbb3863%5E%21/#F22 Link: https://android.googlesource.com/kernel/msm/+/54837652e3400ecc63ccc78b2193faf4f349a32e%5E%21/#F0 Link: https://android.googlesource.com/kernel/msm/+/f0409b07174ceca217f8b7fd255418feff06092d%5E%21/#F0 Signed-off-by: Richard Acayan Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20221014001934.4995-4-mailingradian@gmail.com Signed-off-by: Linus Walleij

pinctrl: qcom: restrict drivers per ARM/ARM64

2022-10-04T07:33:37+00:00

There is no point to allow selecting pin-controller drivers for Qualcomm ARMv7 SoCs when building ARM64 kernel, and vice versa. This makes kernel configuration more difficult as many do not remember the Qualcomm SoCs. There won't be a single image for ARMv7 and ARMv8/9 SoCs, so no features/options are lost. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220925112103.148836-1-krzysztof.kozlowski@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add sc8280xp lpass lpi pinctrl driver

2022-08-25T12:32:04+00:00

Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SC8280XP. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[189 - 207] --> LPASS LPI GPIO [0 - 18] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220817113747.9111-3-srinivas.kandagatla@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Add sm8450 lpass lpi pinctrl driver

2022-08-25T12:29:56+00:00

Add pinctrl driver to support pin configuration for LPASS (Low Power Audio SubSystem) LPI (Low Power Island) pinctrl on SM8450. This IP is an additional pin control block for Audio Pins on top the existing SoC Top level pin-controller. Hardware setup looks like: TLMM GPIO[165 - 187] --> LPASS LPI GPIO [0 - 22] This pin controller has some similarities compared to Top level msm SoC Pin controller like 'each pin belongs to a single group' and so on. However this one is intended to control only audio pins in particular, which can not be configured/touched by the Top level SoC pin controller except setting them as gpios. Apart from this, slew rate is also available in this block for certain pins which are connected to SLIMbus or SoundWire Bus. Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220817113833.9625-3-srinivas.kandagatla@linaro.org Signed-off-by: Linus Walleij

pinctrl: qcom: Make PINCTRL_SM8450 depend on PINCTRL_MSM

2022-08-03T18:31:14+00:00

All the many other configs depend on config PINCTRL_MSM, yet for config PINCTRL_SM8450 we select config PINCTRL_MSM. Make config PINCTRL_SM8450 depend on PINCTRL_MSM to be consistent with the rest. Signed-off-by: John Garry Suggested-by: Arnd Bergmann Link: https://lore.kernel.org/r/1658829764-124936-1-git-send-email-john.garry@huawei.com Signed-off-by: Linus Walleij