kernel/linux.git/drivers/pinctrl/meson, branch v5.6.17

pinctrl: meson-gxl: fix GPIOX sdio pins

2020-02-21T15:28:16+00:00

In the gxl driver, the sdio cmd and clk pins are inverted. It has not caused any issue so far because devices using these pins always take both pins so the resulting configuration is OK. Fixes: 0f15f500ff2c ("pinctrl: meson: Add GXL pinctrl definitions") Reviewed-by: Jerome Brunet Signed-off-by: Nicolas Belin Link: https://lore.kernel.org/r/1582204512-7582-1-git-send-email-nbelin@baylibre.com Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2020-01-29T17:51:36+00:00

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes, nothing too exciting about this. Some changes hit arch/sh and arch/arm but are well isolated and acknowledged by the respective arch maintainers. Core changes: - Dropped the chained IRQ setup callback into GPIOLIB as we got rid of the last users of that in this changeset. New drivers: - New driver for Ingenic X1830. - New driver for Freescale i.MX8MP. Driver enhancements: - Fix all remaining Intel drivers to pass their IRQ chips along with the GPIO chips. - Intel Baytrail allocates its irqchip dynamically. - Intel Lynxpoint is thoroughly rewritten and modernized. - Aspeed AST2600 pin muxing and configuration is much improved. - Qualcomm SC7180 functions are updated and wakeup interrupt map is provided. - A whole slew of Renesas SH-PFC cleanups and improvements. - Fix up the Intel DT bindings to use the generic YAML DT bindings schema (a first user of this)" * tag 'pinctrl-v5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (99 commits) pinctrl: madera: Remove extra blank line pinctrl: qcom: Don't lock around irq_set_irq_wake() pinctrl: mvebu: armada-37xx: use use platform api gpio: Drop the chained IRQ handler assign function pinctrl: freescale: Add i.MX8MP pinctrl driver support dt-bindings: imx: Add pinctrl binding doc for i.MX8MP pinctrl: tigerlake: Tiger Lake uses _HID enumeration pinctrl: sunrisepoint: Add Coffee Lake-S ACPI ID pinctrl: iproc: Use platform_get_irq_optional() to avoid error message pinctrl: dt-bindings: Fix some errors in the lgm and pinmux schema pinctrl: intel: Pass irqchip when adding gpiochip pinctrl: intel: Add GPIO <-> pin mapping ranges via callback pinctrl: baytrail: Replace WARN with dev_info_once when setting direct-irq pin to output pinctrl: baytrail: Do not clear IRQ flags on direct-irq enabled pins pinctrl: sunrisepoint: Add missing Interrupt Status register offset pinctrl: sh-pfc: Split R-Car H3 support in two independent drivers pinctrl: artpec6: fix __iomem on reg in set pinctrl: ingenic: Use devm_platform_ioremap_resource() pinctrl: ingenic: Factorize irq_set_type function pinctrl: ingenic: Remove duplicated ingenic_chip_info structures ...

pinctrl: meson: meson8b: add the GPIOH pinmux settings for ETH_RXD{2,3}

2020-01-07T12:57:17+00:00

GPIOH_5 and GPIOH_6 can have two Ethernet related functions: - GPIOH_5 can be ETH_TXD1 or ETH_RXD3 - GPIOH_6 can be ETH_TXD0 or ETH_RXD2 Add the bits for eth_rxd3_h and eth_rxd2_h so the ETH_RXD function can be disabled when using the ETH_TXD function of GPIOH_{5,6}. No problem was observed so far, but in theory this could lead to two different signals being routed to the same pad (which could break Ethernet). These settings were found in the public "Amlogic Ethernet controller user guide": http://openlinux.amlogic.com/@api/deki/files/75/=Amlogic_Ethenet_controller_user_Guide.pdf Signed-off-by: Martin Blumenstingl Link: https://lore.kernel.org/r/20191226191425.3797490-1-martin.blumenstingl@googlemail.com Reviewed-by: Neil Armstrong Signed-off-by: Linus Walleij

pinctrl: meson: Fix wrong shift value when get drive-strength

2020-01-07T10:21:07+00:00

In meson_pinconf_get_drive_strength, variable bit is calculated by meson_calc_reg_and_bit, this value is the offset from the first pin of a certain bank to current pin, while Meson SoCs use two bits for each pin to depict drive-strength. So a left shift by 1 should be done or node pinconf-pins shows wrong message. Fixes: 6ea3e3bbef37 ("pinctrl: meson: add support of drive-strength-microamp") Signed-off-by: Qianggui Song Link: https://lore.kernel.org/r/20191226023734.9631-1-qianggui.song@amlogic.com Signed-off-by: Linus Walleij

pinctrl: meson-axg: Use the correct style for SPDX License Identifier

2019-12-12T10:33:06+00:00

This patch corrects the SPDX License Identifier style in header file related Meson axg SoC pinctrl driver. It assigns explicit block comment for the SPDX License Identifier. Changes made by using a script provided by Joe Perches here: https://lkml.org/lkml/2019/2/7/46. Suggested-by: Joe Perches Signed-off-by: Nishad Kamdar Link: https://lore.kernel.org/r/bcb86aa22d8d8499502bbd8c54a364be24886a86.1574871463.git.nishadkamdar@gmail.com Signed-off-by: Linus Walleij

pinctrl: meson: add pinctrl driver support for Meson-A1 SoC

2019-11-19T14:55:26+00:00

Meson A1 SoC share the same register layout of pinmux with previous Meson-G12A, however there is difference for gpio and pin config register in A1. The main difference is that registers before A1 are grouped by function while those of A1 are by bank. The new register layout is as below: /* first bank */ /* addr */ - P_PADCTRL_GPIOP_I base + 0x00 << 2 - P_PADCTRL_GPIOP_O base + 0x01 << 2 - P_PADCTRL_GPIOP_OEN base + 0x02 << 2 - P_PADCTRL_GPIOP_PULL_EN base + 0x03 << 2 - P_PADCTRL_GPIOP_PULL_UP base + 0x04 << 2 - P_PADCTRL_GPIOP_DS base + 0x05 << 2 /* second bank */ - P_PADCTRL_GPIOB_I base + 0x10 << 2 - P_PADCTRL_GPIOB_O base + 0x11 << 2 - P_PADCTRL_GPIOB_OEN base + 0x12 << 2 - P_PADCTRL_GPIOB_PULL_EN base + 0x13 << 2 - P_PADCTRL_GPIOB_PULL_UP base + 0x14 << 2 - P_PADCTRL_GPIOB_DS base + 0x15 << 2 Each bank contains at least 6 registers to be configured, if one bank has more than 16 gpios, an extra P_PADCTRL_GPIO[X]_DS_EXT is included. Between two adjacent P_PADCTRL_GPIO[X]_I, there is an offset 0x10, that is to say, for third bank, the offsets will be 0x20,0x21,0x22,0x23,0x24 ,0x25 according to above register layout. For previous chips, registers are grouped according to their functions while registers of A1 are according to bank.Also note that there is no AO bank any more in A1. Current Meson pinctrl driver can cover such change by using base address of GPIO as that of drive-strength. While simply giving reg_ds = reg_pullen make wrong value to reg_ds for Socs that do not support drive-strength like AXG.To make things simple, add an extra dt parser function for a1 and remain the old dt parser function for only reg parsing. Signed-off-by: Qianggui Song Link: https://lore.kernel.org/r/1573819429-6937-3-git-send-email-qianggui.song@amlogic.com Reviewed-by: Neil Armstrong Signed-off-by: Linus Walleij

pinctrl: meson: add a new callback for SoCs fixup

2019-11-19T14:53:58+00:00

pinctrl: meson-gxbb: Fix wrong pinning definition for uart_c

2019-09-13T12:40:41+00:00

Hi i tried to use the uart_C of the the odroid-c2. I enabled it in the dts file. During boot it crashed when the the sdcard slot is addressed. After long search in the net i found this: https://forum.odroid.com/viewtopic.php?f=139&t=25371&p=194370&hilit=uart_C#p177856 After changing the pin definitions accordingly erverything works. Uart_c is functioning and sdcard ist working. Fixes: 6db0f3a8a04e46 ("pinctrl: amlogic: gxbb: add more UART pins") Signed-off-by: Otto Meier Link: https://lore.kernel.org/r/1cc32a18-464d-5531-7a1c-084390e2ecb1@gmx.net Signed-off-by: Linus Walleij

pinctrl: meson: meson: Add of_node_put() before return

2019-08-23T09:48:08+00:00

Each iteration of for_each_child_of_node puts the previous node, but in the case of a return from the middle of the loop, there is no put, thus causing a memory leak. Hence add an of_node_put before the return. Issue found with Coccinelle. Signed-off-by: Nishka Dasgupta Link: https://lore.kernel.org/r/20190815060718.3286-1-nishkadg.linux@gmail.com Reviewed-by: Neil Armstrong Signed-off-by: Linus Walleij

pinctrl: meson-g12a: add pwm_a on GPIOE_2 pinmux

2019-08-05T11:00:54+00:00

Add the missing pinmux for the pwm_a function on the GPIOE_2 pin. Reviewed-by: Kevin Hilman Reviewed-by: Martin Blumenstingl Signed-off-by: Neil Armstrong Link: https://lore.kernel.org/r/20190729125838.6498-1-narmstrong@baylibre.com Signed-off-by: Linus Walleij