Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v7.0-rc7 2026-03-19T18:52:22+00:00 2026-03-19T18:52:22+00:00 Luca Leonardo Scorcia l.scorcia@gmail.com 2026-03-17T11:02:06+00:00 urn:sha1:8f9f64c8f90dca07d3b9f1d7ce5d34ccd246c9dd Some pinctrl devices like mt6397 or mt6392 don't support EINT at all, but the mtk_eint_init function is always called and returns -ENODEV, which then bubbles up and causes probe failure. To address this only call mtk_eint_init if EINT pins are present. Tested on Xiaomi Mi Smart Clock x04g (mt6392). Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Luca Leonardo Scorcia <l.scorcia@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 2026-02-16T17:35:24+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-02-16T17:35:24+00:00 urn:sha1:46a1daac56b3bf1bdbd8b37e6db811f015bc1f4b Pull pin control updates from Linus Walleij: "Core changes: - Drop the unused devm_pinctrl_unregister() function - Move pretended generic pin control functionality out of the core and into the Amlogic AM4 driver. We have something better coming (hopefully) New hardware support: - Spacemit K3 (RISC-V) pin control support - Atmel AT91 PIO4 (ARM32) SAMA7D65 pin control support - Exynos9610 (ARM64) pin control support - Qualcomm Mahua TLMM (ARM64) pin control support - Microchip Polarfire MSSIO (RISC-V) pin control support - Ocelot LAN9645XF (multiplatform) pin control support Improvements: - Using a few more guards for locking - Various nonurgent fixes and tweaks" * tag 'pinctrl-v7.0-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (73 commits) pinctrl: generic: move function to amlogic-am4 driver pinctrl: intel: Align Copyright note with corporate guidelines pinctrl: mediatek: remove unused drv_offset field pinctrl: canaan: k230: Fix NULL pointer dereference when parsing devicetree pinctrl: single: fix refcount leak in pcs_add_gpio_func() pinctrl: meson: amlogic-a4: Fix device node reference leak in bank helpers pinctrl: qcom: sm8250-lpass-lpi: Fix i2s2_data_groups definition pinctrl: core: Remove duplicate error messages pinctrl: core: Simplify devm_pinctrl_*() pinctrl: core: Remove unused devm_pinctrl_unregister() dt-bindings: pinctrl: spacemit: fix drive-strength check warning pinctrl: fix kismet issues with GENERIC_PINCTRL pinctrl: tangier: Join tng_pinctrl_probe() into its wrapper pinctrl: tangier: Remove duplicate error messages pinctrl: lynxpoint: Remove duplicate error messages pinctrl: cherryview: Remove duplicate error messages pinctrl: baytrail: Remove duplicate error messages pinctrl: intel: Remove duplicate error messages pinctrl: equilibrium: Fix device node reference leak in pinbank_init() dt-bindings: pinctrl: pinctrl-microchip-sgpio: add LAN969x ... 2026-02-03T00:33:25+00:00 Akari Tsuyukusa akkun11.open@gmail.com 2026-01-11T05:30:24+00:00 urn:sha1:ca3299dc3d6d9791c7e4a9bb7474150e66a525fe The 'drv_offset' member in 'struct mtk_pinctrl_devdata' has been unused since the driver's inception. Drive strength control for MediaTek pinctrl drivers is actually configured via 'pin_drv_grp', making this specific offset field redundant. Remove the unused field from the common 'mtk_pinctrl_devdata' structure and its corresponding initialization in the mt8365 driver to clean up the code and avoid confusion. Signed-off-by: Akari Tsuyukusa <akkun11.open@gmail.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 2026-01-27T09:02:35+00:00 Shiji Yang yangshiji66@outlook.com 2026-01-17T03:04:37+00:00 urn:sha1:6da9f0cc2717158857f8b8b9369523d0d6770c07 The MT798x series SoCs have IES regiter definitions. I think we must enable the ies_present flag to correctly configure the pin input mode. Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 2025-12-26T18:13:01+00:00 Liang Jie liangjie@lixiang.com 2025-12-09T10:02:17+00:00 urn:sha1:255b721c96046d4c57fa2268e4c72607868ce91f mtk_eint_do_init() allocates several pointer arrays which are then populated in a per-instance loop and freed on error. The arrays are currently allocated with devm_kmalloc(), so their entries are left uninitialised until the per-instance allocations succeed. On a failure in the middle of the loop, the error path iterates over the full nbase range and calls devm_kfree() on each element. For indices which were never initialised, the corresponding array entries contain stack garbage. If any of those happen to be non-zero, devm_kfree() will pass them to devres_destroy(), which will WARN because there is no matching devm_kmalloc() resource for such bogus pointers. Improve the robustness and readability by: - Using devm_kcalloc() for the pointer arrays so that all entries start as NULL, ensuring that only genuinely initialised elements may be freed and preventing spurious WARN_ON()s in the error path. - Switching the allocations to sizeof(*ptr) / sizeof(**ptr) forms, avoiding hard-coded element types and making the code more resilient to future type changes. - Dropping the redundant NULL checks before devm_kfree(), as devm_kfree() safely handles NULL pointers. The functional behaviour in the successful initialisation path remains unchanged, while the error handling becomes simpler and less error-prone. Reviewed-by: fanggeng <fanggeng@lixiang.com> Signed-off-by: Liang Jie <liangjie@lixiang.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 2025-12-26T17:45:11+00:00 Louis-Alexis Eyraud louisalexis.eyraud@collabora.com 2025-12-03T11:32:42+00:00 urn:sha1:fa917d3d570279dc3d699cbd947d0da0fde2e402 In mt8189-pinctrl driver, a previous commit changed the register base name array (mt8189_pinctrl_register_base_names) entry name and order to align it with the same name and order as the "mediatek,mt8189-pinctrl" devicetree bindings. The new order (by ascending register address) now causes an issue with MT8189 pinctrl configuration. MT8189 SoC has multiple base addresses for the pin configuration registers. Several constant data structures, declaring each pin configuration, are using PIN_FIELD_BASE() macro which i_base parameter indicates for a given pin the lookup index in the base register address array of the driver internal data for the configuration register read/write accesses. But in practice, this parameter is given a hardcoded numerical value that corresponds to the expected base register entry index in mt8189_pinctrl_register_base_names array. Since this array reordering, the i_base index matching is no more correct. So, in order to avoid modifying over a thousand of PIN_FIELD_BASE() calls, restore previous mt8189_pinctrl_register_base_names entry order. Fixes: 518919276c41 ("pinctrl: mediatek: mt8189: align register base names to dt-bindings ones") Signed-off-by: Louis-Alexis Eyraud <louisalexis.eyraud@collabora.com> Signed-off-by: Linus Walleij <linusw@kernel.org> 2025-12-08T21:45:00+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-12-08T21:45:00+00:00 urn:sha1:a110f942672c8995dc1cacb5a44c6730856743aa Pull pin control updates from Linus Walleij: "The technical details below. For me the CIX Semi and Axis Communications ARTPEC-9 SoCs were the most interesting new drivers in this merge window. Core changes: - Handle per-direction skew control in the generic pin config - Drop the pointless subsystem boilerplate banner message during boot. Less noise in the console. It's available as debug message if someone really want it New drivers: - Samsung Exynos 8890 SoC support - Samsung Exynos derived Axis Communications ARTPEC-9 SoC support. These guys literally live next door to me, ARTPEC spells out "Axis Real-Time Picture Encoding Chip" and is tailored for camera image streams and is something they have evolved for a quarter of a century - Mediatek MT6878 SoC support - Qualcomm Glymur PMIC support (mostly just compatible strings) - Qualcomm Kaanapali SoC TLMM support - Microchip pic64gx "gpio2" SoC support - Microchip Polarfire "iomux0" SoC support - CIX Semiconductors SKY1 SoC support - Rockchip RK3506 SoC support - Airhoa AN7583 chip support Improvements: - Improvements for ST Microelectronics STM32 handling of skew settings so input and output can have different skew settings - A whole bunch of device tree binding cleanups: Marvell Armada and Berlin, Actions Semiconductor S700 and S900, Broadcom Northstar 2 (NS2), Bitmain BM1880 and Spreadtrum SC9860 are moved over to schema" * tag 'pinctrl-v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (107 commits) pinctrl: add CONFIG_OF dependencies for microchip drivers pinctrl: starfive: use dynamic GPIO base allocation pinctrl: single: Fix incorrect type for error return variable MAINTAINERS: Change Linus Walleij mail address pinctrl: cix: Fix obscure dependency dt-bindings: pinctrl: cix,sky1-pinctrl: Drop duplicate newline dt-bindings: pinctrl: aspeed,ast2600-pinctrl: Add PCIe RC PERST# group pinctrl: airoha: Fix AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data pinctrl: airoha: fix pinctrl function mismatch issue pinctrl: cherryview: Convert to use intel_gpio_add_pin_ranges() pinctrl: intel: Export intel_gpio_add_pin_ranges() pinctrl: renesas: rzg2l: Refactor OEN register PWPR handling pinctrl: airoha: convert comma to semicolon pinctrl: elkhartlake: Switch to INTEL_GPP() macro pinctrl: cherryview: Switch to INTEL_GPP() macro pinctrl: emmitsburg: Switch to INTEL_GPP() macro pinctrl: denverton: Switch to INTEL_GPP() macro pinctrl: cedarfork: Switch to INTEL_GPP() macro pinctrl: airoha: add support for Airoha AN7583 PINs dt-bindings: pinctrl: airoha: Document AN7583 Pin Controller ... 2025-11-18T23:03:30+00:00 Nathan Chancellor nathan@kernel.org 2025-11-12T18:44:30+00:00 urn:sha1:0341d1b1ebf10bcbb9f35e174e83dbb21068387d Clang warns (or errors with CONFIG_WERROR=y / W=e): pinctrl/mediatek/pinctrl-airoha.c:2064:41: error: variable 'an7583_pinctrl_drive_e2_conf' is not needed and will not be emitted [-Werror,-Wunneeded-internal-declaration] 2064 | static const struct airoha_pinctrl_conf an7583_pinctrl_drive_e2_conf[] = { | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~ Due to a typo, an7583_pinctrl_drive_e2_conf is only used within ARRAY_SIZE() (hence no instance of -Wunused-variable), which is evaluated at compile time, so it will not be needed in the final object file. Fix the .confs assignment for AIROHA_PINCTRL_CONFS_DRIVE_E2 in an7583_pinctrl_match_data to clear up the warning. Closes: https://github.com/ClangBuiltLinux/linux/issues/2142 Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs") Signed-off-by: Nathan Chancellor <nathan@kernel.org> Acked-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2025-11-18T23:02:24+00:00 Chukun Pan amadeus@jmu.edu.cn 2025-11-15T10:00:00+00:00 urn:sha1:f2bd5a0f59d052d16749bccf637690e51947a5d6 The blamed commit made the following changes: -#define PINCTRL_FUNC_DESC(id)... - .desc = PINCTRL_PINFUNCTION(#id, ... +#define PINCTRL_FUNC_DESC(id, table)... + .desc = PINCTRL_PINFUNCTION(#id, ... - PINCTRL_FUNC_DESC(pon)... + PINCTRL_FUNC_DESC("pon", pon)... It's clear that the id of funcs doesn't match the definition. Remove redundant #string from the definition to fix this issue: pinctrl-airoha ...: invalid function mdio in map table Fixes: 4043b0c45f85 ("pinctrl: airoha: generalize pins/group/function/confs handling") Signed-off-by: Chukun Pan <amadeus@jmu.edu.cn> Acked-by: Christian Marangi <ansuelsmth@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 2025-11-12T12:44:14+00:00 Chen Ni nichen@iscas.ac.cn 2025-11-11T06:29:44+00:00 urn:sha1:f2596d9fa19c0910319fe8eb1ccdf6348f0e02db Replace comma between expressions with semicolons. Using a ',' in place of a ';' can have unintended side effects. Although that is not the case here, it is seems best to use ';' unless ',' is intended. Found by inspection. No functional change intended. Compile tested only. Signed-off-by: Chen Ni <nichen@iscas.ac.cn> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>