kernel/linux.git/drivers/pinctrl/mediatek, branch v6.6.132

pinctrl: mediatek: common: Fix probe failure for devices without EINT

2026-04-02T11:07:17+00:00

[ Upstream commit 8f9f64c8f90dca07d3b9f1d7ce5d34ccd246c9dd ] Some pinctrl devices like mt6397 or mt6392 don't support EINT at all, but the mtk_eint_init function is always called and returns -ENODEV, which then bubbles up and causes probe failure. To address this only call mtk_eint_init if EINT pins are present. Tested on Xiaomi Mi Smart Clock x04g (mt6392). Fixes: e46df235b4e6 ("pinctrl: mediatek: refactor EINT related code for all MediaTek pinctrl can fit") Signed-off-by: Luca Leonardo Scorcia Reviewed-by: AngeloGioacchino Del Regno Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: common-v2: Fix broken bias-disable for PULL_PU_PD_RSEL_TYPE

2024-09-04T11:28:23+00:00

[ Upstream commit 166bf8af91225576f85208a31eaedbadd182d1ea ] Despite its name, commit fed74d75277d ("pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPE") actually broke bias-disable for PULL_PU_PD_RSEL_TYPE. mtk_pinconf_bias_set_combo() tries every bias method supported by the pin until one succeeds. For PULL_PU_PD_RSEL_TYPE pins, before the breaking commit, mtk_pinconf_bias_set_rsel() would be called first to try and set the RSEL value (as well as PU and PD), and if that failed, the only other valid option was that bias-disable was specified, which would then be handled by calling mtk_pinconf_bias_set_pu_pd() and disabling both PU and PD. The breaking commit misunderstood this logic and added an early "return 0" in mtk_pinconf_bias_set_rsel(). The result was that in the bias-disable case, the bias was left unchanged, since by returning success, mtk_pinconf_bias_set_combo() no longer tried calling mtk_pinconf_bias_set_pu_pd() to disable the bias. Since the logic for configuring bias-disable on PULL_PU_PD_RSEL_TYPE pins required mtk_pinconf_bias_set_rsel() to fail first, in that case, an error was printed to the log, eg: mt8195-pinctrl 10005000.pinctrl: Not support rsel value 0 Ohm for pin = 29 (GPIO29) This is what the breaking commit actually got rid of, and likely part of the reason why that commit was thought to be fixing functionality, while in reality it was breaking it. Instead of simply reverting that commit, restore the functionality but in a way that avoids the error from being printed and makes the code less confusing: * Return 0 explicitly if a bias method was successful * Introduce an extra function mtk_pinconf_bias_set_pu_pd_rsel() that calls both mtk_pinconf_bias_set_rsel() (only if needed) and mtk_pinconf_bias_set_pu_pd() * And analogously for the corresponding getters Fixes: fed74d75277d ("pinctrl: mediatek: common-v2: Fix bias-disable for PULL_PU_PD_RSEL_TYPE") Signed-off-by: Nícolas F. R. A. Prado Link: https://lore.kernel.org/20240808-mtk-rsel-bias-disable-fix-v1-1-1b4e85bf596c@collabora.com Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: paris: Rework support for PIN_CONFIG_{INPUT,OUTPUT}_ENABLE

2024-05-17T10:01:57+00:00

[ Upstream commit c5d3b64c568a344e998830e0e94a7c04e372f89b ] There is a misinterpretation of some of the PIN_CONFIG_* options in this driver library. PIN_CONFIG_OUTPUT_ENABLE should refer to a buffer or switch in the output direction of the electrical path. The MediaTek hardware does not have such a thing. The driver incorrectly maps this option to the GPIO function's direction. Likewise, PIN_CONFIG_INPUT_ENABLE should refer to a buffer or switch in the input direction. The hardware does have such a mechanism, and is mapped to the IES bit. The driver however sets the direction in addition to the IES bit, which is incorrect. On readback, the IES bit isn't even considered. Ironically, the driver does not support readback for PIN_CONFIG_OUTPUT, while its readback of PIN_CONFIG_{INPUT,OUTPUT}_ENABLE is what it should be doing for PIN_CONFIG_OUTPUT. Rework support for these three options, so that PIN_CONFIG_OUTPUT_ENABLE is completely removed, PIN_CONFIG_INPUT_ENABLE is only linked to the IES bit, and PIN_CONFIG_OUTPUT is linked to the GPIO function's direction and output level. Fixes: 805250982bb5 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Message-ID: <20240327091336.3434141-3-wenst@chromium.org> Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: paris: Fix PIN_CONFIG_INPUT_SCHMITT_ENABLE readback

2024-05-17T10:01:57+00:00

[ Upstream commit 08f66a8edd08f6f7cfa769c81634b29a2b123908 ] In the generic pin config library, readback of some options are handled differently compared to the setting of those options: the argument value is used to convey enable/disable of an option in the set path, but success or -EINVAL is used to convey if an option is enabled or disabled in the debugfs readback path. PIN_CONFIG_INPUT_SCHMITT_ENABLE is one such option. Fix the readback of the option in the mediatek-paris library, so that the debugfs dump is not showing "input schmitt enabled" for pins that don't have it enabled. Fixes: 1bea6afbc842 ("pinctrl: mediatek: Refine mtk_pinconf_get()") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Message-ID: <20240327091336.3434141-2-wenst@chromium.org> Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: Drop bogus slew rate register range for MT8192

2024-03-26T22:19:45+00:00

[ Upstream commit e15ab05a6b3ed42f2f43f8bd1a1abdbde64afecd ] The MT8192 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: d32f38f2a8fc ("pinctrl: mediatek: Add pinctrl driver for mt8192") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131071910.3950450-2-wenst@chromium.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: Drop bogus slew rate register range for MT8186

2024-03-26T22:19:45+00:00

[ Upstream commit 3a29c87548809405bcbc66acc69cbe6f15184d94 ] The MT8186 does not support configuring pin slew rate. This is evident from both the datasheet, and the fact that the driver points the slew rate register range at the GPIO direction register range. Drop the bogus setting. Fixes: 8b483bda1e46 ("pinctrl: add pinctrl driver on mt8186") Signed-off-by: Chen-Yu Tsai Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240131071910.3950450-1-wenst@chromium.org Signed-off-by: Linus Walleij Signed-off-by: Sasha Levin

pinctrl: mediatek: assign functions to configure pin bias on MT7986

2023-08-21T10:39:11+00:00

Assign bias_disable_get/set and bias_get/set functions to allow configuring pin bias on MT7986. Fixes: 2c58d8dc9cd0 ("pinctrl: mediatek: add pull_type attribute for mediatek MT7986 SoC") Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/47f72372354312a839b9337e09476aadcc206e8b.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij

pinctrl: mediatek: fix pull_type data for MT7981

2023-08-21T10:39:11+00:00

MediaTek has released pull_type data for MT7981 in their SDK. Use it and set functions to configure pin bias. Fixes: 6c83b2d94fcc ("pinctrl: add mt7981 pinctrl driver") Signed-off-by: Daniel Golle Link: https://lore.kernel.org/r/7bcc8ead25dbfabc7f5a85d066224a926fbb4941.1692327317.git.daniel@makrotopia.org Signed-off-by: Linus Walleij

pinctrl: Explicitly include correct DT includes

2023-07-20T19:41:24+00:00

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Reviewed-by: Damien Le Moal Acked-by: Emil Renner Berthing Acked-by: Geert Uytterhoeven Link: https://lore.kernel.org/r/20230714174901.4062397-1-robh@kernel.org Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2023-05-02T22:40:41+00:00

Pull pin control updates from Linus Walleij: "Mostly drivers! Nothing special: some new Qualcomm chips as usual, and the new NXP S32 and nVidia BlueField-3. Core changes: - Make a lot of pin controllers with GPIO and irqchips immutable, i.e. not living structs, but const structs. This is driving a changed initiated by the irqchip maintainers. New drivers: - New driver for the NXP S32 SoC pin controller - As part of a thorough cleanup and restructuring of the Ralink/Mediatek drivers, the Ralink MIPS pin control drivers were folded into the Mediatek directory and the family is renamed "mtmips". The Ralink chips live on as Mediatek MIPS family where new variants can be added. As part of this work also the device tree bindings were reworked. - New subdriver for the Qualcomm SM7150 SoC. - New subdriver for the Qualcomm IPQ9574 SoC. - New driver for the nVidia BlueField-3 SoC. - Support for the Qualcomm PMM8654AU mixed signal circuit GPIO. - Support for the Qualcomm PMI632 mixed signal circuit GPIO. Improvements: - Add some missing pins and generic cleanups on the Renesas r8a779g0 and r8a779g0 pin controllers. Generic Renesas extension for power source selection on several SoCs. - Misc cleanups for the Atmel AT91 and AT91-PIO4 pin controllers - Make the GPIO mode work on the Qualcomm SM8550-lpass-lpi driver. - Several device tree binding cleanups as the binding YAML syntax is solidifying" * tag 'pinctrl-v6.4-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (153 commits) pinctrl-bcm2835.c: fix race condition when setting gpio dir dt-bindings: pinctrl: qcom,sm8150: Drop duplicate function value "atest_usb2" dt-bindings: pinctrl: qcom: Add few missing functions pinctrl: qcom: spmi-gpio: Add PMI632 support dt-bindings: pinctrl: qcom,pmic-gpio: add PMI632 pinctrl: wpcm450: select MFD_SYSCON pinctrl: qcom ssbi-gpio: Convert to immutable irq_chip pinctrl: qcom ssbi-mpp: Convert to immutable irq_chip pinctrl: qcom spmi-mpp: Convert to immutable irq_chip pinctrl: plgpio: Convert to immutable irq_chip pinctrl: pistachio: Convert to immutable irq_chip pinctrl: pic32: Convert to immutable irq_chip pinctrl: sx150x: Convert to immutable irq_chip pinctrl: stmfx: Convert to immutable irq_chip pinctrl: st: Convert to immutable irq_chip pinctrl: mcp23s08: Convert to immutable irq_chip pinctrl: equilibrium: Convert to immutable irq_chip pinctrl: npcm7xx: Convert to immutable irq_chip pinctrl: armada-37xx: Convert to immutable irq_chip pinctrl: nsp: Convert to immutable irq_chip ...