kernel/linux.git/drivers/pinctrl/mediatek, branch v5.15.7

Merge tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2021-09-02T21:22:56+00:00

Pull pin control updates from Linus Walleij: "This is the bulk of pin control changes for the v5.15 kernel cycle, no core changes at all this time, just driver work! New drivers: - New subdriver for Intel Keem Bay (an ARM-based SoC) - New subdriver for Qualcomm MDM9607 and SM6115 - New subdriver for ST Microelectronics STM32MP135 - New subdriver for Freescale i.MX8ULP ("Ultra Low Power") - New subdriver for Ingenic X2100 - Support for Qualcomm PMC8180, PMC8180C, SA8155p-adp PMIC GPIO - Support Samsung Exynos850 - Support Renesas RZ/G2L Enhancements: - A major refactoring of the Rockchip driver, breaking part of it out to a separate GPIO driver in drivers/gpio - Pin bias support on Renesas r8a77995 - Add SCI pins support to Ingenic JZ4755 and JZ4760 - Mediatek device tree bindings converted to YAML" * tag 'pinctrl-v5.15-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (53 commits) pinctrl: renesas: Add RZ/G2L pin and gpio controller driver pinctrl: samsung: Add Exynos850 SoC specific data dt-bindings: pinctrl: samsung: Add Exynos850 doc MAINTAINERS: Add maintainers for amd-pinctrl driver pinctrl: Add Intel Keem Bay pinctrl driver dt-bindings: pinctrl: Add bindings for Intel Keembay pinctrl driver pinctrl: zynqmp: Drop pinctrl_unregister for devm_ registered device dt-bindings: pinctrl: qcom-pmic-gpio: Remove the interrupts property dt-bindings: pinctrl: qcom-pmic-gpio: Convert qcom pmic gpio bindings to YAML dt-bindings: pinctrl: mt8195: Use real world values for drive-strength arguments dt-bindings: mediatek: convert pinctrl to yaml arm: dts: mt8183: Move pinfunc to include/dt-bindings/pinctrl arm: dts: mt8135: Move pinfunc to include/dt-bindings/pinctrl pinctrl: ingenic: Add .max_register in regmap_config pinctrl: ingenic: Fix bias config for X2000(E) pinctrl: ingenic: Fix incorrect pull up/down info pinctrl: Ingenic: Add pinctrl driver for X2100. dt-bindings: pinctrl: Add bindings for Ingenic X2100. pinctrl: Ingenic: Add SSI pins support for JZ4755 and JZ4760. pinctrl: Ingenic: Improve the code. ...

Merge tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

2021-08-30T21:38:37+00:00

Pull irq updates from Thomas Gleixner: "Updates to the interrupt core and driver subsystems: Core changes: - The usual set of small fixes and improvements all over the place, but nothing stands out MSI changes: - Further consolidation of the PCI/MSI interrupt chip code - Make MSI sysfs code independent of PCI/MSI and expose the MSI interrupts of platform devices in the same way as PCI exposes them. Driver changes: - Support for ARM GICv3 EPPI partitions - Treewide conversion to generic_handle_domain_irq() for all chained interrupt controllers - Conversion to bitmap_zalloc() throughout the irq chip drivers - The usual set of small fixes and improvements" * tag 'irq-core-2021-08-30' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (57 commits) platform-msi: Add ABI to show msi_irqs of platform devices genirq/msi: Move MSI sysfs handling from PCI to MSI core genirq/cpuhotplug: Demote debug printk to KERN_DEBUG irqchip/qcom-pdc: Trim unused levels of the interrupt hierarchy irqdomain: Export irq_domain_disconnect_hierarchy() irqchip/gic-v3: Fix priority comparison when non-secure priorities are used irqchip/apple-aic: Fix irq_disable from within irq handlers pinctrl/rockchip: drop the gpio related codes gpio/rockchip: drop irq_gc_lock/irq_gc_unlock for irq set type gpio/rockchip: support next version gpio controller gpio/rockchip: use struct rockchip_gpio_regs for gpio controller gpio/rockchip: add driver for rockchip gpio dt-bindings: gpio: change items restriction of clock for rockchip,gpio-bank pinctrl/rockchip: add pinctrl device to gpio bank struct pinctrl/rockchip: separate struct rockchip_pin_bank to a head file pinctrl/rockchip: always enable clock for gpio controller genirq: Fix kernel doc indentation EDAC/altera: Convert to generic_handle_domain_irq() powerpc: Bulk conversion to generic_handle_domain_irq() nios2: Bulk conversion to generic_handle_domain_irq() ...

pinctrl: Bulk conversion to generic_handle_domain_irq()

2021-08-12T10:39:39+00:00

Wherever possible, replace constructs that match either generic_handle_irq(irq_find_mapping()) or generic_handle_irq(irq_linear_revmap()) to a single call to generic_handle_domain_irq(). Acked-by: Krzysztof Kozlowski Acked-by: Linus Walleij Signed-off-by: Marc Zyngier

pinctrl: mediatek: fix platform_no_drv_owner.cocci warnings

2021-07-23T16:11:30+00:00

drivers/pinctrl/mediatek/pinctrl-mt8365.c:488:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Generated by: scripts/coccinelle/api/platform_no_drv_owner.cocci Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") CC: Fabien Parent Reported-by: kernel test robot Signed-off-by: kernel test robot Link: https://lore.kernel.org/r/20210626051550.GA37544@d0c207d51ce8 Signed-off-by: Linus Walleij

pinctrl: mediatek: Fix fallback behavior for bias_set_combo

2021-07-23T15:41:56+00:00

Some pin doesn't support PUPD register, if it fails and fallbacks with bias_set_combo case, it will call mtk_pinconf_bias_set_pupd_r1_r0() to modify the PUPD pin again. Since the general bias set are either PU/PD or PULLSEL/PULLEN, try bias_set or bias_set_rev1 for the other fallback case. If the pin doesn't support neither PU/PD nor PULLSEL/PULLEN, it will return -ENOTSUPP. Fixes: 81bd1579b43e ("pinctrl: mediatek: Fix fallback call path") Signed-off-by: Hsin-Yi Wang Reviewed-by: Chen-Yu Tsai Reviewed-by: Zhiyong Tao Link: https://lore.kernel.org/r/20210701080955.2660294-1-hsinyi@chromium.org Signed-off-by: Linus Walleij

pinctrl: mediatek: fix mode encoding

2021-06-09T13:30:45+00:00

Pin modes are encoded in the SoC data structure. Use that value to set IES SMT. Cc: Fabien Parent Cc: Sean Wang Cc: Mattijs Korpershoek Cc: linux-mediatek@lists.infradead.org Fixes: 696beef77521 ("pinctrl: mediatek: move bit assignment") Signed-off-by: Matthias Brugger Signed-off-by: Matthias Brugger Link: https://lore.kernel.org/r/20210608150656.29007-1-matthias.bgg@kernel.org Signed-off-by: Linus Walleij

pinctrl: mtk: Fix mt8365 Kconfig dependency

2021-06-07T06:56:20+00:00

This SoC needs to select PINCTRL_MTK or we can end up in kernel compiles that miss some symbols. Cc: Fabien Parent Reported-by: kernel test robot Fixes: e94d8b6fb83a ("pinctrl: mediatek: add support for mt8365 SoC") Signed-off-by: Linus Walleij

pinctrl: mediatek: move bit assignment

2021-05-28T09:19:10+00:00

The bit needs offset to be defined which happens some lines below. Looks like a bug. The kernel test robot complains: drivers/pinctrl/mediatek/pinctrl-mtk-common.c:137:12: warning: variable 'offset' is uninitialized when used here [-Wuninitialized] bit = BIT(offset & pctl->devdata->mode_mask); ^~~~~~ Fix it up by reverting to what was done before. Cc: Fabien Parent Cc: Sean Wang Cc: Matthias Brugger Cc: Mattijs Korpershoek Cc: linux-mediatek@lists.infradead.org Fixes: 9f940d8ecf92 ("pinctrl: mediatek: don't hardcode mode encoding in common code") Reported-by: kernel test robot Signed-off-by: Linus Walleij

pinctrl: mediatek: add support for mt8365 SoC

2021-05-27T14:50:15+00:00

Add pinctrl driver for MT8365 SoC. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519162409.3755679-3-fparent@baylibre.com Signed-off-by: Linus Walleij

pinctrl: mediatek: don't hardcode mode encoding in common code

2021-05-27T14:50:15+00:00

MT8365 encode the pins mode differently than other MTK pinctrl drivers that use the PINCTRL_MTK common code. Add 3 new fields in mtk_pinctrl_devdata in order to store how pin modes are encoded into the register. At the same time update all the pinctrl driver that depends on CONFIG_PINCTRL_MTK. Signed-off-by: Fabien Parent Link: https://lore.kernel.org/r/20210519162409.3755679-2-fparent@baylibre.com Signed-off-by: Linus Walleij