<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/pinctrl/intel/Kconfig, branch v5.6.17</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.6.17</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.6.17'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2019-12-13T14:48:49+00:00</updated>
<entry>
<title>pinctrl: lynxpoint: Switch to pin control API</title>
<updated>2019-12-13T14:48:49+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-11-25T17:30:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=64e14e90646cafa9940cead9f7ba336c55671bf9'/>
<id>urn:sha1:64e14e90646cafa9940cead9f7ba336c55671bf9</id>
<content type='text'>
When all preparations are done, we may switch to pin control API.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: lynxpoint: Move GPIO driver to pin controller folder</title>
<updated>2019-12-13T14:48:47+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-08-22T15:40:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=eb83479e18999e34b3b800f54aa31137f7f41c33'/>
<id>urn:sha1:eb83479e18999e34b3b800f54aa31137f7f41c33</id>
<content type='text'>
Move Lynxpoint GPIO driver under Intel pin control umbrella
for further transformation to a real pin control driver.

Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Intel Tiger Lake pin controller support</title>
<updated>2019-10-30T14:05:18+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2019-10-21T16:45:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=c9ccf71fc8073b8d3a484751585088ff14c8d762'/>
<id>urn:sha1:c9ccf71fc8073b8d3a484751585088ff14c8d762</id>
<content type='text'>
This driver adds pinctrl/GPIO support for Intel Tiger Lake SoC. The
GPIO controller is based on the next generation GPIO hardware but still
compatible with the one supported by the Intel core pinctrl/GPIO driver.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Convert to use SPDX identifier</title>
<updated>2018-07-02T13:52:10+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2018-06-29T12:36:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=875a92b3f58a117842c0f9e8d65355c6be218fa2'/>
<id>urn:sha1:875a92b3f58a117842c0f9e8d65355c6be218fa2</id>
<content type='text'>
Reduce size of duplicated comments by switching to use SPDX identifier.

No functional change.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Ice Lake PCH pin controller support</title>
<updated>2018-06-29T12:51:26+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2018-06-27T12:05:53+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e6800d2601fafb51f5feb3c216c884c2efb4c77d'/>
<id>urn:sha1:e6800d2601fafb51f5feb3c216c884c2efb4c77d</id>
<content type='text'>
This adds pinctrl/GPIO support for Intel Ice Lake PCH. The Ice Lake PCH
GPIO is based on the same version of the Intel GPIO hardware than Intel
Cannon Lake with different set of pins and ACPI ID.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Intel Cedar Fork PCH pin controller support</title>
<updated>2017-10-31T09:11:21+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2017-10-23T12:40:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0f80dbc133e3ebf82766b5276d8d0fe998a6f0db'/>
<id>urn:sha1:0f80dbc133e3ebf82766b5276d8d0fe998a6f0db</id>
<content type='text'>
Intel Cedar Fork PCH is the successor of Intel Denverton PCH but it is
based on the newer GPIO/pinctrl hardware block. Add a new pinctrl/GPIO
driver to support it.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Do not depend in GPIOLIB, select it</title>
<updated>2017-10-12T07:15:33+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2017-10-11T10:04:35+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e2a021d4491c4ce0f8b082121951d8c59260ed5d'/>
<id>urn:sha1:e2a021d4491c4ce0f8b082121951d8c59260ed5d</id>
<content type='text'>
Instead of depends on GPIOLIB and having to run around in
Kconfig menus looking for why your device is not available,
simply select it from the pin control drivers that need it.

The Kconfig for GPIOLIB is improved, selectable and this
should "just work".

Cc: Phil Reid &lt;preid@electromag.com.au&gt;
Cc: Sebastian Reichel &lt;sebastian.reichel@collabora.co.uk&gt;
Cc: Peter Rosin &lt;peda@axentia.se&gt;
Cc: Andrey Smirnov &lt;andrew.smirnov@gmail.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Intel Lewisburg GPIO support</title>
<updated>2017-08-22T13:42:19+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2017-08-18T10:05:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e480b745386e3911c45e5b281f3471c7aff8cc3b'/>
<id>urn:sha1:e480b745386e3911c45e5b281f3471c7aff8cc3b</id>
<content type='text'>
Intel Lewisburg has the same GPIO hardware than Intel Sunrisepoint-H
except few differences in register offsets and pin lists. Because of
this we add a separate pinctrl driver for Lewisburg.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: Add Intel Denverton pin controller support</title>
<updated>2017-08-14T13:01:59+00:00</updated>
<author>
<name>Mika Westerberg</name>
<email>mika.westerberg@linux.intel.com</email>
</author>
<published>2017-08-03T16:36:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=75bb10b479c33a8e15ab99d6f35a141e86df8547'/>
<id>urn:sha1:75bb10b479c33a8e15ab99d6f35a141e86df8547</id>
<content type='text'>
This driver adds pinctrl/GPIO support for Intel Denverton SoC. The GPIO
controller is based on the same hardware design that is already used in
Intel Sunrisepoint so we leverage the core driver here.

Signed-off-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Reviewed-by: Andy Shevchenko &lt;andy.shevchenko@gmail.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: intel: wrap Intel pin control drivers in an architecture check</title>
<updated>2017-08-14T13:01:02+00:00</updated>
<author>
<name>Peter Robinson</name>
<email>pbrobinson@gmail.com</email>
</author>
<published>2017-07-04T06:49:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=29ddbb8101b267b3b8b4a8708bf228fc4c182df6'/>
<id>urn:sha1:29ddbb8101b267b3b8b4a8708bf228fc4c182df6</id>
<content type='text'>
The Intel pin control drivers are architecture specific so add an if arch
to check for X86 or compile test to ensure continued test coverage.

Signed-off-by: Peter Robinson &lt;pbrobinson@gmail.com&gt;
Reviewed-by: Heikki Krogerus &lt;heikki.krogerus@linux.intel.com&gt;
Acked-by: Mika Westerberg &lt;mika.westerberg@linux.intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
