kernel/linux.git/drivers/pinctrl/aspeed, branch v6.19.11

pinctrl: aspeed-g6: Add PCIe RC PERST pin group

2025-07-23T11:22:41+00:00

The PCIe RC PERST uses SSPRST# as PERST# and enable this pin to output. Signed-off-by: Jacky Chou Acked-by: Linus Walleij Link: https://lore.kernel.org/20250715034320.2553837-8-jacky_chou@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed: Constify static 'pinctrl_desc'

2025-06-18T11:26:36+00:00

The local static 'struct pinctrl_desc' is not modified, so can be made const for code safety. Reviewed-by: Andrew Jeffery Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/20250611-pinctrl-const-desc-v2-5-b11c1d650384@linaro.org Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Support drive-strength for GPIOF/G

2024-10-28T12:58:43+00:00

Add drive strength configuration support for GPIO F and G groups. Signed-off-by: Billy Tsai Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/20241023104406.4083460-1-billy_tsai@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed-g6: Add NCSI pin group config

2024-06-26T10:41:07+00:00

Based on the NCSI pin table (Table 181) in NCSI spec[1], the reference clock output pin (RMIIXRCLKO) is not needed on the management controller side. To optimize pin usage, add new NCSI pin group that excludes RMIIXRCLKO, reducing the number of required pins. LINK: [1] https://www.dmtf.org/sites/default/files/standards/documents/DSP0222_1.2.0a.pdf Signed-off-by: Potin Lai Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/20240621093142.698529-3-potin.lai.pt@gmail.com Signed-off-by: Linus Walleij

Merge tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

2024-04-30T15:50:58+00:00

Pull pin control fixes from Linus Walleij: - Fix a double-free in the pinctrl_enable() errorpath - Fix a refcount leak in pinctrl_dt_to_map() - Fix selecting the GPIO pin control state and the UART3 pin config group in the Intel Baytrail driver - Fix readback of schmitt trigger status in the Mediatek Paris driver, along with some semantic pin config issues in this driver - Fix a pin suffix typo in the Meson A1 driver - Fix an erroneous register offset in he Aspeed G6 driver - Fix an inconsistent lock state and the interrupt type on resume in the Renesas RZG2L driver - Fix some minor confusion in the Renesas DT bindings * tag 'pinctrl-v6.9-2' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: pinctrl: renesas: rzg2l: Configure the interrupt type on resume pinctrl: devicetree: fix refcount leak in pinctrl_dt_to_map() pinctrl: baytrail: Add pinconf group for uart3 pinctrl: baytrail: Fix selecting gpio pinctrl state pinctrl: mediatek: paris: Rework support for PIN_CONFIG_{INPUT,OUTPUT}_ENABLE pinctrl: mediatek: paris: Fix PIN_CONFIG_INPUT_SCHMITT_ENABLE readback pinctrl: core: delete incorrect free in pinctrl_enable() pinctrl/meson: fix typo in PDM's pin name pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T pinctrl: renesas: rzg2l: Execute atomically the interrupt configuration dt-bindings: pinctrl: renesas,rzg2l-pinctrl: Allow 'input' and 'output-enable' properties

kbuild: make -Woverride-init warnings more consistent

2024-03-31T02:32:26+00:00

The -Woverride-init warn about code that may be intentional or not, but the inintentional ones tend to be real bugs, so there is a bit of disagreement on whether this warning option should be enabled by default and we have multiple settings in scripts/Makefile.extrawarn as well as individual subsystems. Older versions of clang only supported -Wno-initializer-overrides with the same meaning as gcc's -Woverride-init, though all supported versions now work with both. Because of this difference, an earlier cleanup of mine accidentally turned the clang warning off for W=1 builds and only left it on for W=2, while it's still enabled for gcc with W=1. There is also one driver that only turns the warning off for newer versions of gcc but not other compilers, and some but not all the Makefiles still use a cc-disable-warning conditional that is no longer needed with supported compilers here. Address all of the above by removing the special cases for clang and always turning the warning off unconditionally where it got in the way, using the syntax that is supported by both compilers. Fixes: 2cd3271b7a31 ("kbuild: avoid duplicate warning options") Signed-off-by: Arnd Bergmann Acked-by: Hamza Mahfooz Acked-by: Jani Nikula Acked-by: Andrew Jeffery Signed-off-by: Jani Nikula Reviewed-by: Linus Walleij Signed-off-by: Masahiro Yamada

pinctrl: pinctrl-aspeed-g6: Fix register offset for pinconf of GPIOR-T

2024-03-28T09:15:15+00:00

The register offset to disable the internal pull-down of GPIOR~T is 0x630 instead of 0x620, as specified in the Ast2600 datasheet v15 The datasheet can download from the official Aspeed website. Fixes: 15711ba6ff19 ("pinctrl: aspeed-g6: Add AST2600 pinconf support") Reported-by: Delphine CC Chiu Signed-off-by: Billy Tsai Reviewed-by: Paul Menzel Reviewed-by: Andrew Jeffery Message-ID: <20240313092809.2596644-1-billy_tsai@aspeedtech.com> Signed-off-by: Linus Walleij

pinctrl: aspeed: Allow changing SPI mode from hardware strap defaults

2023-10-10T12:01:30+00:00

Some platforms unfortunately have their SPI mode selection bits strapped incorrectly (such as being configured for passthrough mode when master mode is in fact the only useful configuration for it) and thus require correction in software. Add the SPI mode bits to the GPIO passthrough bits as the exceptions to the read-only rule for the hardware strap register so that the pinctrl subsystem can be used for such corrections. Signed-off-by: Zev Weiss Reviewed-by: Andrew Jeffery Link: https://lore.kernel.org/r/20231005030849.11352-2-zev@bewilderbeest.net Signed-off-by: Linus Walleij

pinctrl: pinctrl-aspeed-g6: Add more settings for USB2AHP function

2023-09-25T12:32:39+00:00

AST2600 USB2AHP (USB PortA: PCIe EHCI to PHY) function needs to set the register SCUC20[16]. Set it to enable the PCIe EHCI device on PCIe bus. Besides, also add USB2AHP signal expressions into pin declarations. Signed-off-by: Joe Wang Link: https://lore.kernel.org/r/20230920103332.274151-1-joe_wang@aspeedtech.com Signed-off-by: Linus Walleij

pinctrl: aspeed: Revert "Force to disable the function's signal"

2023-01-30T22:51:03+00:00

This reverts commit cf517fef601b9dde151f0afc27164d13bf1fd907. The commit cf517fef601b ("pinctrl: aspeed: Force to disable the function's signal") exposed a problem with fetching the regmap for reading the GFX register. The Romulus machine the device tree contains a gpio hog for GPIO S7. With the patch applied: Muxing pin 151 for GPIO Disabling signal VPOB9 for VPO aspeed-g5-pinctrl 1e6e2080.pinctrl: Failed to acquire regmap for IP block 1 aspeed-g5-pinctrl 1e6e2080.pinctrl: request() failed for pin 151 The code path is aspeed-gpio -> pinmux-g5 -> regmap -> clk, and the of_clock code returns an error as it doesn't have a valid struct clk_hw pointer. The regmap call happens because pinmux wants to check the GFX node (IP block 1) to query bits there. For reference, before the offending patch: Muxing pin 151 for GPIO Disabling signal VPOB9 for VPO Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000 Disabling signal VPOB9 for VPOOFF1 Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000 Disabling signal VPOB9 for VPOOFF2 Want SCU8C[0x00000080]=0x1, got 0x0 from 0x00000000 Enabling signal GPIOS7 for GPIOS7 Muxed pin 151 as GPIOS7 gpio-943 (seq_cont): hogged as output/low We can't skip the clock check to allow pinmux to proceed, because the write to disable VPOB9 will try to set a bit in the GFX register space which will not stick when the IP is in reset. However, we do not want to enable the IP just so pinmux can do a disable-enable dance for the pin. For now, revert the offending patch while a correct solution is found. Fixes: cf517fef601b ("pinctrl: aspeed: Force to disable the function's signal") Link: https://github.com/openbmc/linux/issues/218 Signed-off-by: Joel Stanley Link: https://lore.kernel.org/r/20230130220845.917985-1-joel@jms.id.au Signed-off-by: Linus Walleij