<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/pinctrl/Makefile, branch linux-5.11.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.11.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-5.11.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2020-12-16T23:02:49+00:00</updated>
<entry>
<title>Merge tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl</title>
<updated>2020-12-16T23:02:49+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2020-12-16T23:02:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f68e4041ef63f03091e44b4eebf1ab5c5d427e6f'/>
<id>urn:sha1:f68e4041ef63f03091e44b4eebf1ab5c5d427e6f</id>
<content type='text'>
Pull pin control updates from Linus Walleij:
 "This is the bulk of pin control changes for the v5.11 kernel.

  Drivers, drivers and drivers. Not a single core change.

  Some new stuff, especially a bunch of new Intel, Qualcomm and Ocelot
  SoCs.

  As part of the modularization attempt, I applied one patch affecting
  the firmware subsystem as a functional (not syntactic/semantic)
  dependency and then it blew up in our face, so I had to revert it,
  bummer. It will come in later, through that subsystem, I guess.

  New drivers:

   - New driver for the Microchip Serial GPIO "SGPIO".

   - Qualcomm SM8250 LPASS (Low Power Audio Subsystem) GPIO driver.

  New subdrivers:

   - Intel Lakefield subdriver.

   - Intel Elkhart Lake subdriver.

   - Intel Alder Lake-S subdriver.

   - Qualcomm MSM8953 subdriver.

   - Qualcomm SDX55 subdriver.

   - Qualcomm SDX55 PMIC subdriver.

   - Ocelot Luton SoC subdriver.

   - Ocelot Serval SoC subdriver.

  Modularization:

   - The Meson driver can now be built as modules.

   - The Qualcomm driver(s) can now be built as modules.

  Incremental improvements:

   - The Intel driver now supports pin configuration for GPIO-related
     configurations.

   - A bunch of Renesas PFC drivers have been augmented with support for
     QSPI pins, groups and functions.

   - Non-critical fixes to the irq handling in the Allwinner Sunxi
     driver"

* tag 'pinctrl-v5.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (80 commits)
  pinctrl/spear: simplify the return expression of spear300_pinctrl_probe()
  pinctrl: mediatek: simplify the return expression of mtk_pinconf_bias_disable_set_rev1()
  dt-bindings: pinctrl: pinctrl-microchip-sgpio: Add irq support
  pinctrl: pinctrl-microchip-sgpio: Add irq support (for sparx5)
  pinctrl: qcom: Add sm8250 lpass lpi pinctrl driver
  dt-bindings: pinctrl: qcom: Add sm8250 lpass lpi pinctrl bindings
  pinctrl: qcom-pmic-gpio: Add support for pmx55
  dt-bindings: pinctrl: qcom-pmic-gpio: Add pmx55 support
  pinctrl: pinctrl-microchip-sgpio: Mark some symbols with static keyword
  pinctrl: at91-pio4: Make PINCTRL_AT91PIO4 depend on HAS_IOMEM to fix build error
  pinctrl: mtk: Fix low level output voltage issue
  pinctrl: falcon: add missing put_device() call in pinctrl_falcon_probe()
  pinctrl: actions: pinctrl-s500: Constify s500_padinfo[]
  pinctrl: pinctrl-microchip-sgpio: Add OF config dependency
  pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO
  dt-bindings: pinctrl: Add bindings for pinctrl-microchip-sgpio driver
  pinctrl: at91-pio4: add support for fewer lines on last PIO bank
  pinctrl: sunxi: Always call chained_irq_{enter, exit} in sunxi_pinctrl_irq_handler
  pinctrl: sunxi: Mark the irq bank not found in sunxi_pinctrl_irq_handler() with WARN_ON
  pinctrl: sunxi: fix irq bank map for the Allwinner A100 pin controller
  ...
</content>
</entry>
<entry>
<title>pinctrl: ralink: add a pinctrl driver for the rt2880 family</title>
<updated>2020-12-08T08:58:01+00:00</updated>
<author>
<name>Sergio Paracuellos</name>
<email>sergio.paracuellos@gmail.com</email>
</author>
<published>2020-12-08T07:55:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=518b466a21ad7fa1e338fa4ed9d180ef439d3bc0'/>
<id>urn:sha1:518b466a21ad7fa1e338fa4ed9d180ef439d3bc0</id>
<content type='text'>
These Socs have 1-3 banks of 8-32 gpios. Rather then setting the muxing of each
pin individually, these socs have mux groups that when set will effect 1-N pins.
Pin groups have a 2, 4 or 8 different muxes.

Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Sergio Paracuellos &lt;sergio.paracuellos@gmail.com&gt;
Link: https://lore.kernel.org/r/20201208075523.7060-3-sergio.paracuellos@gmail.com
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: pinctrl-microchip-sgpio: Add pinctrl driver for Microsemi Serial GPIO</title>
<updated>2020-12-01T23:09:48+00:00</updated>
<author>
<name>Lars Povlsen</name>
<email>lars.povlsen@microchip.com</email>
</author>
<published>2020-11-13T14:51:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7e5ea974e61c8dd0832dcfe931ef959b2eb02587'/>
<id>urn:sha1:7e5ea974e61c8dd0832dcfe931ef959b2eb02587</id>
<content type='text'>
This adds a pinctrl driver for the Microsemi/Microchip Serial GPIO
(SGPIO) device used in various SoC's.

The driver is added as a pinctrl driver, albeit only having just GPIO
support currently. The hardware supports other functions that will be
added following.

Signed-off-by: Lars Povlsen &lt;lars.povlsen@microchip.com&gt;
Link: https://lore.kernel.org/r/20201113145151.68900-3-lars.povlsen@microchip.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'renesas-pinctrl-for-v5.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel</title>
<updated>2020-09-21T21:43:30+00:00</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2020-09-21T21:43:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e777f8c8f9f6a3fe4f42f5f101620adc60b78616'/>
<id>urn:sha1:e777f8c8f9f6a3fe4f42f5f101620adc60b78616</id>
<content type='text'>
pinctrl: renesas: Updates for v5.10

  - Add CAN and USB1 PWEN pin groups on R-Car H2 and RZ/G1,
  - Three more conversion of DT bindings to json-schema,
  - Group all Renesas pinctrl drivers and improve visual Kconfig
    structure,
  - Rename drivers/pinctrl/sh-pfc to drivers/pinctrl/renesas,
  - Minor fixes and improvements.
</content>
</entry>
<entry>
<title>pinctrl: Rename sh-pfc to renesas</title>
<updated>2020-09-15T08:04:35+00:00</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2020-09-09T13:15:33+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=077365a941166f3a7f5894017f9d26d17cdec00e'/>
<id>urn:sha1:077365a941166f3a7f5894017f9d26d17cdec00e</id>
<content type='text'>
The drivers/pinctrl/sh-pfc subdirectory was originally created to group
pin control drivers for various Renesas SuperH and SH-Mobile platforms.
However, the name "sh-pfc" no longer reflects its contents, as the
directory now contains pin control drivers for Renesas SuperH, ARM32,
and ARM64 SoCs.

Hence rename the subdirectory from drivers/pinctrl/sh-pfc to
drivers/pinctrl/renesas, and the related Kconfig symbol from
PINCTRL_SH_PFC to PINCTRL_RENESAS.

Rename the git branch in MAINTAINERS, too, for consistency.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Link: https://lore.kernel.org/r/20200909131534.12897-3-geert+renesas@glider.be
</content>
</entry>
<entry>
<title>pinctrl: sh-pfc: Collect Renesas related CONFIGs in one place</title>
<updated>2020-09-15T07:37:20+00:00</updated>
<author>
<name>Kuninori Morimoto</name>
<email>kuninori.morimoto.gx@renesas.com</email>
</author>
<published>2020-08-24T05:49:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=af028ecd546a71b4d3937b63e1b39707ef9c3b17'/>
<id>urn:sha1:af028ecd546a71b4d3937b63e1b39707ef9c3b17</id>
<content type='text'>
Renesas related pinctrl CONFIGs are located in many places, which is
confusing.
This patch collects them into the same place, grouped in a new "Renesas
pinctrl drivers" menu.
This patch also moves pinctrl-rz{a1,a2,n1}.c into the sh-pfc folder.

Signed-off-by: Kuninori Morimoto &lt;kuninori.morimoto.gx@renesas.com&gt;
Link: https://lore.kernel.org/r/87k0xoy4r7.wl-kuninori.morimoto.gx@renesas.com
[geert: Update path in MAINTAINERS]
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>pinctrl: visconti: Add Toshiba Visconti SoCs pinctrl support</title>
<updated>2020-09-12T10:25:53+00:00</updated>
<author>
<name>Nobuhiro Iwamatsu</name>
<email>nobuhiro1.iwamatsu@toshiba.co.jp</email>
</author>
<published>2020-09-09T20:43:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=a68a7844264e4fb91dcc1c6525cdb275223ce79c'/>
<id>urn:sha1:a68a7844264e4fb91dcc1c6525cdb275223ce79c</id>
<content type='text'>
Add pinctrl support to Toshiba Visconti SoCs.

Signed-off-by: Nobuhiro Iwamatsu &lt;nobuhiro1.iwamatsu@toshiba.co.jp&gt;
Reviewed-by: Punit Agrawal &lt;punit1.agrawal@toshiba.co.jp&gt;
Link: https://lore.kernel.org/r/20200909204336.2558-3-nobuhiro1.iwamatsu@toshiba.co.jp
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: mcp23s08: Split to three parts: core, I²C, SPI</title>
<updated>2020-04-16T12:21:23+00:00</updated>
<author>
<name>Andy Shevchenko</name>
<email>andriy.shevchenko@linux.intel.com</email>
</author>
<published>2020-04-07T17:38:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0f04a81784fe3ddc00cae74c517265b3ddb8825c'/>
<id>urn:sha1:0f04a81784fe3ddc00cae74c517265b3ddb8825c</id>
<content type='text'>
Split the driver to three parts: core, I²C, SPI.
No functional change intended.

Signed-off-by: Andy Shevchenko &lt;andriy.shevchenko@linux.intel.com&gt;
Link: https://lore.kernel.org/r/20200407173849.43628-9-andriy.shevchenko@linux.intel.com
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: da9062: add driver support</title>
<updated>2020-02-19T16:16:31+00:00</updated>
<author>
<name>Marco Felsch</name>
<email>m.felsch@pengutronix.de</email>
</author>
<published>2020-01-08T10:47:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=56cc3af4e8c8eaba91b51efa6081a868adbd97c3'/>
<id>urn:sha1:56cc3af4e8c8eaba91b51efa6081a868adbd97c3</id>
<content type='text'>
The DA9062 is a mfd pmic device which supports 5 GPIOs. The GPIOs can
be used as input, output or have a special use-case.

The patch adds the support for the normal input/output use-case.

Signed-off-by: Marco Felsch &lt;m.felsch@pengutronix.de&gt;
Link: https://lore.kernel.org/r/20200108104746.1765-4-m.felsch@pengutronix.de
Reviewed-by: Adam Thomson &lt;Adam.Thomson.Opensource@diasemi.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: Add pinmux &amp; GPIO controller driver for a new SoC</title>
<updated>2019-11-21T13:47:44+00:00</updated>
<author>
<name>Rahul Tanwar</name>
<email>rahul.tanwar@linux.intel.com</email>
</author>
<published>2019-11-15T09:25:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=1948d5c51dba4e4e2652a5687991a6460d78b5d0'/>
<id>urn:sha1:1948d5c51dba4e4e2652a5687991a6460d78b5d0</id>
<content type='text'>
Intel Lightning Mountain SoC has a pinmux controller &amp; GPIO controller IP which
controls pin multiplexing &amp; configuration including GPIO functions selection &amp;
GPIO attributes configuration.

This IP is not based on &amp; does not have anything in common with Chassis
specification. The pinctrl drivers under pinctrl/intel/* are all based upon
Chassis spec compliant pinctrl IPs. So this driver doesn't fit &amp; can not use
pinctrl framework under pinctrl/intel/* and it requires a separate new driver.

Add a new GPIO &amp; pin control framework based driver for this IP.

Signed-off-by: Rahul Tanwar &lt;rahul.tanwar@linux.intel.com&gt;
Link: https://lore.kernel.org/r/33e649758b70490f01724a887c490d5008c7656d.1573797249.git.rahul.tanwar@linux.intel.com
Reviewed-by: Andy Shevchenko &lt;andriy.shevchenko@intel.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
