kernel/linux.git/drivers/phy/ti, branch v6.1.87

phy: ti: phy-omap-usb2: Fix NULL pointer dereference for SRP

2024-02-16T18:06:25+00:00

[ Upstream commit 7104ba0f1958adb250319e68a15eff89ec4fd36d ] If the external phy working together with phy-omap-usb2 does not implement send_srp(), we may still attempt to call it. This can happen on an idle Ethernet gadget triggering a wakeup for example: configfs-gadget.g1 gadget.0: ECM Suspend configfs-gadget.g1 gadget.0: Port suspended. Triggering wakeup ... Unable to handle kernel NULL pointer dereference at virtual address 00000000 when execute ... PC is at 0x0 LR is at musb_gadget_wakeup+0x1d4/0x254 [musb_hdrc] ... musb_gadget_wakeup [musb_hdrc] from usb_gadget_wakeup+0x1c/0x3c [udc_core] usb_gadget_wakeup [udc_core] from eth_start_xmit+0x3b0/0x3d4 [u_ether] eth_start_xmit [u_ether] from dev_hard_start_xmit+0x94/0x24c dev_hard_start_xmit from sch_direct_xmit+0x104/0x2e4 sch_direct_xmit from __dev_queue_xmit+0x334/0xd88 __dev_queue_xmit from arp_solicit+0xf0/0x268 arp_solicit from neigh_probe+0x54/0x7c neigh_probe from __neigh_event_send+0x22c/0x47c __neigh_event_send from neigh_resolve_output+0x14c/0x1c0 neigh_resolve_output from ip_finish_output2+0x1c8/0x628 ip_finish_output2 from ip_send_skb+0x40/0xd8 ip_send_skb from udp_send_skb+0x124/0x340 udp_send_skb from udp_sendmsg+0x780/0x984 udp_sendmsg from __sys_sendto+0xd8/0x158 __sys_sendto from ret_fast_syscall+0x0/0x58 Let's fix the issue by checking for send_srp() and set_vbus() before calling them. For USB peripheral only cases these both could be NULL. Fixes: 657b306a7bdf ("usb: phy: add a new driver for omap usb2 phy") Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20240128120556.8848-1-tony@atomide.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select()

2023-05-11T14:03:37+00:00

[ Upstream commit 57c0e1362fdd57d0cea7ab1e583b58abf4bd8c2d ] In the wiz_mode_select() function, the configuration performed for PHY_TYPE_USXGMII is unreachable. Fix it. Fixes: b64a85fb8f53 ("phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver") Signed-off-by: Siddharth Vadapalli Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230403094552.929108-1-s-vadapalli@ti.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: ti: fix Kconfig warning and operator precedence

2023-02-01T07:34:08+00:00

[ Upstream commit 7124c93887cc4e6c5b48920f83115e4a5892e870 ] Fix Kconfig depends operator precedence to prevent a Kconfig warning: WARNING: unmet direct dependencies detected for MUX_MMIO Depends on [n]: MULTIPLEXER [=m] && OF [=n] Selected by [m]: - PHY_AM654_SERDES [=m] && (OF [=n] && ARCH_K3 || COMPILE_TEST [=y]) && COMMON_CLK [=y] Fixes: 71e2f5c5c224 ("phy: ti: Add a new SERDES driver for TI's AM654x SoC") Fixes: 091876cc355d ("phy: ti: j721e-wiz: Add support for WIZ module present in TI J721E SoC") Signed-off-by: Randy Dunlap Cc: Vinod Koul Cc: Kishon Vijay Abraham I Cc: linux-phy@lists.infradead.org Cc: Arnd Bergmann Link: https://lore.kernel.org/r/20230110062529.22668-1-rdunlap@infradead.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: ti: phy-j721e-wiz: fix reference leaks in wiz_probe()

2022-09-24T06:29:37+00:00

These two error paths need to call of_node_put(child_node) before returning. Fixes: edd473d4293a ("phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g") Fixes: 7ae14cf581f2 ("phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver") Signed-off-by: Dan Carpenter Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/YyxFI8aW23IC/21U@kili Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: stop name conflict if multiple serdes are initialized

2022-09-20T06:46:52+00:00

When multiple serdes instances are initialized the first will succeed but additional will conflict over clocks names and probing fails. Signed-off-by: Matt Ranostay Signed-off-by: Vignesh Raghavendra Link: https://lore.kernel.org/r/20220909200026.3422-1-mranostay@ti.com Signed-off-by: Vinod Koul

phy: ti: gmii-sel: Add support for CPSW5G GMII SEL in J7200

2022-09-13T17:40:26+00:00

Each of the CPSW5G ports in J7200 support additional modes like QSGMII. Add a new compatible for J7200 to support the additional modes. In TI's J7200, each of the CPSW5G ethernet interfaces can act as a QSGMII or QSGMII-SUB port. The QSGMII interface is responsible for performing auto-negotiation between the MAC and the PHY while the rest of the interfaces are designated as QSGMII-SUB interfaces, indicating that they will not be taking part in the auto-negotiation process. To indicate the interface which will serve as the main QSGMII interface, add a property "ti,qsgmii-main-ports", whose value indicates the port number of the interface which shall serve as the main QSGMII interface. The rest of the interfaces are then assigned QSGMII-SUB mode by default. The property "ti,qsgmii-main-ports" is used to configure the CTRLMMR_ENETx_CTRL register. Depending on the device, it is possible for more than one QSGMII main port to exist. Thus, the property "ti,qsgmii-main-ports" is defined as an array of values in order to reuse the property for other devices. Signed-off-by: Siddharth Vadapalli Link: https://lore.kernel.org/r/20220912085650.83263-4-s-vadapalli@ti.com Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: set PMA_CMN_REFCLK_DIG_DIV based on reflk rate

2022-08-30T05:12:58+00:00

For J7200-SR2.0 and AM64 we don't model Common refclock divider as a clock divider as the divisor rate is fixed based on operating reference clock frequency. We just program the recommended value into the register. This simplifies the device tree and implementation a lot. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-8-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: add support for j7200-wiz-10g

2022-08-30T05:12:58+00:00

j7200-wiz-10g supports 2 reference clocks. However, the control bits for these clocks is in a separate register that sits in the System Control register space. Handle that register. Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-7-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz.c: Add usxgmii support in wiz driver

2022-08-30T05:12:57+00:00

Changes the wiz_p_mac_div_sel() and wiz_mode_select() to configure serdes for USXGMII. Adds the support to configure mac_src_sel, refclk_sel and rxfclk_sel in the LANECTL register and configures the serdes for usxgmii. [rogerq] Fix MAC_SRC_SEL to 0x3 for USXGMII as per CSL code. Signed-off-by: Tanmay Patil Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-4-rogerq@kernel.org Signed-off-by: Vinod Koul

phy: ti: phy-j721e-wiz: Add SGMII support in wiz driver for J7200

2022-08-30T05:12:57+00:00

Select the same mac divider for SGMII too as the one being used for QSGMII. Enable full rate divider configuration support for J721E_WIZ_10G for SGMII. Signed-off-by: Siddharth Vadapalli Signed-off-by: Vignesh Raghavendra Signed-off-by: Roger Quadros Link: https://lore.kernel.org/r/20220628122255.24265-2-rogerq@kernel.org Signed-off-by: Vinod Koul