kernel/linux.git/drivers/phy/samsung, branch v6.12.80

phy: exynos5-usbdrd: fix EDS distribution tuning (gs101)

2025-05-29T09:02:51+00:00

[ Upstream commit 21860f340ba76ee042e5431ff92537f89bc11476 ] This code's intention is to configure lane0 and lane2 tunings, but for lane2 there is a typo and it ends up tuning something else. Fix the typo, as it doesn't appear to make sense to apply different tunings for lane0 vs lane2. The same typo appears to exist in the bootloader, hence we restore the original value in the typo'd registers as well. This can be removed once / if the bootloader is updated. Note that this is incorrect in the downstream driver as well - the values had been copied from there. Reviewed-by: Peter Griffin Tested-by: Peter Griffin Signed-off-by: André Draszik Tested-by: Will McVicker Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-4-f5961268b149@linaro.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: exynos5-usbdrd: gs101: ensure power is gated to SS phy in phy_exit()

2025-03-07T17:25:42+00:00

commit 8789b4296aa796f658a19cac7d27365012893de1 upstream. We currently don't gate the power to the SS phy in phy_exit(). Shuffle the code slightly to ensure the power is gated to the SS phy as well. Fixes: 32267c29bc7d ("phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)") CC: stable@vger.kernel.org # 6.11+ Reviewed-by: Krzysztof Kozlowski Reviewed-by: Peter Griffin Signed-off-by: André Draszik Link: https://lore.kernel.org/r/20241205-gs101-usb-phy-fix-v4-1-0278809fb810@linaro.org Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman

phy: exynos5-usbdrd: fix MPLL_MULTIPLIER and SSC_REFCLKSEL masks in refclk

2025-03-07T17:25:42+00:00

commit e2158c953c973adb49383ddea2504faf08d375b7 upstream. In exynos5_usbdrd_{pipe3,utmi}_set_refclk(), the masks PHYCLKRST_MPLL_MULTIPLIER_MASK and PHYCLKRST_SSC_REFCLKSEL_MASK are not inverted when applied to the register values. Fix it. Cc: stable@vger.kernel.org Fixes: 59025887fb08 ("phy: Add new Exynos5 USB 3.0 PHY driver") Signed-off-by: Kaustabh Chakraborty Reviewed-by: Krzysztof Kozlowski Reviewed-by: Anand Moon Link: https://lore.kernel.org/r/20250209-exynos5-usbdrd-masks-v1-1-4f7f83f323d7@disroot.org Signed-off-by: Vinod Koul Signed-off-by: Greg Kroah-Hartman

Merge tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2024-09-23T21:05:10+00:00

Pull phy updates from Vinod Koul: "New hw support: - Rcar usb2 support for RZ/G3S SoC - Nuvoton MA35 SoC USB 2.0 PHY driver Removed: - obsolete qcom,usb-8x16-phy bindings Updates: - 4 lane PCIe support for Qualcomm X1E80100 - Constify structure in subsystem update - Subsystem simplification with scoped for each OF child loop update - Yaml conversion for Qualcomm sata phy, Hiilicon hi3798cv200-combphy bindings" * tag 'phy-for-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (40 commits) phy: renesas: rcar-gen3-usb2: Add support for the RZ/G3S SoC dt-bindings: phy: renesas,usb2-phy: Document RZ/G3S phy bindings phy: renesas: rcar-gen3-usb2: Add support to initialize the bus phy: ti: j721e-wiz: Simplify with scoped for each OF child loop phy: ti: j721e-wiz: Drop OF node reference earlier for simpler code phy: ti: gmii-sel: Simplify with dev_err_probe() phy: ti: am654-serdes: Use scoped device node handling to simplify error paths phy: qcom: qmp-pcie-msm8996: Simplify with scoped for each OF child loop phy: mediatek: xsphy: Simplify with scoped for each OF child loop phy: mediatek: tphy: Simplify with scoped for each OF child loop phy: hisilicon: usb2: Simplify with scoped for each OF child loop phy: cadence: sierra: Simplify with scoped for each OF child loop phy: broadcom: brcm-sata: Simplify with scoped for each OF child loop phy: broadcom: bcm-cygnus-pcie: Simplify with scoped for each OF child loop phy: nuvoton: add new driver for the Nuvoton MA35 SoC USB 2.0 PHY dt-bindings: phy: nuvoton,ma35-usb2-phy: add new bindings phy: qcom: qmp-pcie: Configure all tables on port B PHY phy: airoha: adjust initialization delay in airoha_pcie_phy_init() dt-bindings: phy: socionext,uniphier: add top-level constraints phy: qcom: qmp-pcie: Add Gen4 4-lanes mode for X1E80100 ...

phy: exynos5-usbdrd: fix error code in probe()

2024-08-04T17:34:06+00:00

Return negative -ENOMEM instead of positive ENOMEM. Fixes: 497ddafe915e ("phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk") Signed-off-by: Dan Carpenter Reviewed-by: Peter Griffin Reviewed-by: André Draszik Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/a956a3e2-c6ce-4f07-ad80-ec8a96e00d16@stanley.mountain Signed-off-by: Vinod Koul

phy: exynos5-usbdrd: convert some FIELD_PREP_CONST() to FIELD_PREP()

2024-07-31T11:12:23+00:00

Use of FIELD_PREP_CONST() was a thinko - it's meant to be used for (constant) initialisers, not constant values. Use FIELD_PREP() where possible. It has better error checking and is therefore the preferred macro to use in those cases. Signed-off-by: André Draszik Reviewed-by: Sam Protsenko Link: https://lore.kernel.org/r/20240710-phy-field-prep-v1-1-2fa3f7dc4fc7@linaro.org Signed-off-by: Vinod Koul

phy: exynos5-usbdrd: support Exynos USBDRD 3.1 combo phy (HS & SS)

2024-07-02T13:22:05+00:00

Add support for the Exynos USB 3.1 DRD combo phy, as found in Exynos 9 SoCs like Google GS101. It supports USB SS, HS and DisplayPort. In terms of UTMI+, this is very similar to the existing Exynos850 support in this driver. The difference is that this combo phy supports both UTMI+ (HS) and PIPE3 (SS). It also supports DP alt mode. The number of ports for UTMI+ and PIPE3 can be determined using the LINKPORT register (which also exists on Exynos E850). For SuperSpeed (SS) a new SS phy is in use and its PIPE3 interface is new compared to Exynos E850, and also very different from the existing support for older Exynos SoCs in this driver. The SS phy needs a bit more configuration work and register tuning for signal quality to work reliably, presumably due to the higher frequency, e.g. to account for different board layouts. Additionally, power needs to be enabled before writing to the SS phy registers. This commit adds the necessary changes for USB HS and SS to work. DisplayPort is out of scope in this commit. Notes: * For the register tuning, exynos5_usbdrd_apply_phy_tunes() has been added with the appropriate data structures to support tuning at various stages during initialisation. Since these are hardware specific, the platform data is supposed to be populated accordingly. The implementation is loosely modelled after the Samsung UFS PHY driver. There is one tuning state for UTMI+, PTS_UTMI_POSTINIT, to execute after init and generally intended for HS signal tuning, as done in this commit. PTS_PIPE3_PREINIT PTS_PIPE3_INIT PTS_PIPE3_POSTINIT PTS_PIPE3_POSTLOCK are tuning states for PIPE3. In the downstream driver, preinit differs by Exynos SoC, and postinit and postlock are different per board. The latter haven't been implemented for gs101 here, because downstream doesn't use them on gs101 either. * Signal lock acquisition for SS depends on the orientation of the USB-C plug. Since there currently is no infrastructure to chain connector events to both the USB DWC3 driver and this phy driver, a work-around has been added in exynos5_usbdrd_usbdp_g2_v4_pma_check_cdr_lock() to check both registers if it failed in one of the orientations. * Equally, we can only establish SS speed in one of the connector orientations due to programming differences when selecting the lane mux in exynos5_usbdrd_usbdp_g2_v4_pma_lane_mux_sel(), which really needs to be dynamic, based on the orientation of the connector. * As is, we can establish a HS link using any cable, and an SS link in one orientation of the plug, falling back to HS if the orientation is reversed to the expectation. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin Tested-by: Will McVicker Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-6-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul

phy: exynos5-usbdrd: convert Vbus supplies to regulator_bulk

2024-07-02T13:22:05+00:00

Using the regulator_bulk APIs, the handling of power supplies becomes much simpler. There is no need anymore to check if regulators have been acquired or not, the bulk APIs will do all the work for us. We can also drop the various handles to the individual power supplies in the driver runtime data and instead simply treat them all as one thing. Error cleanup also becomes much simpler. Converting to the regulator_bulk APIs also makes it easier to add support for those SoCs that have additional power supplies for the PHY. Google Tensor gs101 is one example of such a SoC. Otherwise we'd have to add all additional supplies individually via individual calls to regulator_get() and enable/disable handle them all individually, including complicated error handling. That doesn't scale and clutters the code. Just update the code to use the regulator_bulk APIs. Signed-off-by: André Draszik Tested-by: Will McVicker Reviewed-by: Peter Griffin Tested-by: Peter Griffin Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-5-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul

phy: exynos5-usbdrd: convert (phy) register access clock to clk_bulk

2024-07-02T13:22:05+00:00

In preparation for support for additional platforms, convert the phy register access clock to using the clk_bulk interfaces. Newer SoCs like Google Tensor gs101 require additional clocks for access to additional (different) register areas (PHY, PMA, PCS), and converting to clk_bulk simplifies addition of those extra clocks. Signed-off-by: André Draszik Reviewed-by: Peter Griffin Tested-by: Peter Griffin Tested-by: Will McVicker Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-4-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul

phy: exynos5-usbdrd: convert core clocks to clk_bulk

2024-07-02T13:22:04+00:00

Using the clk_bulk APIs, the clock handling for the core clocks becomes much simpler. No need to check any flags whether or not certain clocks exist or not. Further, we can drop the various handles to the individual clocks in the driver data and instead simply treat them all as one thing. So far, this driver assumes that all platforms have a clock "ref". It also assumes that the clocks "phy_pipe", "phy_utmi", and "itp" exist if the platform data "has_common_clk_gate" is set to true. It then goes and individually tries to acquire and enable and disable all the individual clocks one by one. Rather than relying on these implicit clocks and open-coding the clock handling, we can just explicitly spell out the clock names in the different device data and use that information to populate clk_bulk_data, allowing us to use the clk_bulk APIs for managing the clocks. As a side-effect, this change highlighted the fact that exynos5_usbdrd_phy_power_on() forgot to check the result of the clock enable calls. Using the clk_bulk APIs, the compiler now warns when return values are not checked - therefore add the necessary check instead of silently ignoring failures and continuing as if all is OK when it isn't. For consistency, also change a related dev_err() to dev_err_probe() in exynos5_usbdrd_phy_clk_handle() to get consistent error message formatting. Finally, exynos5_usbdrd_phy_clk_handle() prints an error message in all cases as necessary (except for -ENOMEM). There is no need to print another message in its caller (the probe() function), and printing errors during OOM conditions is usually discouraged. Drop the duplicated message in exynos5_usbdrd_phy_probe(). Signed-off-by: André Draszik Tested-by: Will McVicker Reviewed-by: Peter Griffin Tested-by: Peter Griffin Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-3-b66de9ae7424@linaro.org Signed-off-by: Vinod Koul