kernel/linux.git/drivers/phy/rockchip, branch v7.0-rc7

Merge tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2026-02-17T19:40:04+00:00

Pull phy updates from Vinod Koul: "Core: - Add suuport for "rx-polarity" and "tx-polarity" device tree properties and phy common properties to manage this New Support: - Qualcomm Glymur PCIe Gen4 2-lanes PCIe phy, DP and edp phy, USB UNI PHY and SMB2370 eUSB2 repeater. SC8280xp QMP UFS PHY, Kaanapali PCIe phy and QMP PHY, QCS615 QMP USB3+DP PHY and driver support for that. - SpacemiT PCIe/combo PHY and K1 USB2 PHY driver. - HDMI 2.1 FRL configuration support and driver enabling for rockchip samsung-hdptx driver - TI TCAN1046 phy - Renesas RZ/V2H(P) and RZ/V2N usb3 - Mediatek MT8188 hdmi-phy - Google Tensor SoC USB PHY driver - Apple Type-C PHY Updates: - Subsystem conversion for clock round_rate() to determine_rate() - TI USB3 DT schema conversion - Samsung ExynosAutov920 usb3, combo hsphy and ssphy support" * tag 'phy-for-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (143 commits) phy: ti: phy-j721e-wiz: convert from divider_round_rate() to divider_determine_rate() dt-bindings: phy: ti,control-phy-otghs: convert to DT schema dt-bindings: phy: ti,phy-usb3: convert to DT schema phy: tegra: xusb: Remove unused powered_on variable phy: renesas: rcar-gen3-usb2: add regulator dependency phy: GOOGLE_USB: add TYPEC dependency phy: enter drivers/phy/Makefile even without CONFIG_GENERIC_PHY phy: renesas: rcar-gen3-usb2: Use mux-state for phyrst management phy: renesas: rcar-gen3-usb2: Add regulator for OTG VBUS control phy: renesas: rcar-gen3-usb2: Use devm_pm_runtime_enable() phy: renesas: rcar-gen3-usb2: Factor out VBUS control logic dt-bindings: phy: renesas,usb2-phy: Document RZ/G3E SoC dt-bindings: phy: renesas,usb2-phy: Document mux-states property dt-bindings: phy: renesas,usb2-phy: Document USB VBUS regulator phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config phy: rockchip: samsung-hdptx: Drop hw_rate driver data phy: rockchip: samsung-hdptx: Compute clk rate from PLL config phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists ...

phy: rockchip: samsung-hdptx: Add HDMI 2.1 FRL support

2026-01-21T08:41:58+00:00

The PHY is capable of handling four HDMI 2.1 Fixed Rate Link (FRL) lanes, and each one can operate at any of the rates of 3Gbps, 6Gbps, 8Gbps, 10Gbps or 12Gbps. Add the necessary driver changes to support the feature. Co-developed-by: Algea Cao Signed-off-by: Algea Cao Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-11-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Extend rk_hdptx_phy_verify_hdmi_config() helper

2026-01-21T08:41:58+00:00

In order to facilitate introduction of HDMI 2.1 FRL support and to avoid recomputing the link rate after verifying the HDMI configuration given as input, extend rk_hdptx_phy_verify_hdmi_config() by providing an optional output parameter to store the validated configuration. For improved code readability, also rename the existing hdmi input parameter. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-10-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Switch to driver specific HDMI config

2026-01-21T08:41:58+00:00

In preparation to support the FRL operation mode which gets configured via the lanes and rate per lane tuple, switch to a driver specific struct for configuring the link rate and bpc. This simplifies and optimizes the implementation by allowing implicit switches between TMDS and FRL rates, without requiring additional checks of the active PHY mode followed by recalculations of the link rate when operating in FRL mode. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-9-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Drop hw_rate driver data

2026-01-21T08:41:58+00:00

The ->hw_rate member of struct rk_hdptx_phy was mainly used to keep track of the clock rate programmed in hardware and support implementing the ->recalc_rate() callback in hdptx_phy_clk_ops. Computing the clock rate from the actual PHY PLL configuration seems to work reliably, hence remove the now redundant struct member. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-8-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Compute clk rate from PLL config

2026-01-21T08:41:57+00:00

Improve ->recalc_rate() callback of hdptx_phy_clk_ops to calculate the initial clock rate based on the actual PHY PLL configuration as retrieved from the related hardware registers. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-7-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Cleanup *_cmn_init_seq lists

2026-01-21T08:41:57+00:00

Drop redundant reg_sequence entries from rk_hdptx_common_cmn_init_seq[], i.e. those that are either duplicated or overridden in rk_hdptx_tmds_cmn_init_seq[]. Additionally, a few items do not really belong to the former, hence move them to the latter. That's mostly a preparatory step for adding FRL support. No functional changes intended at this point. Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-6-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Enable lane output in common helper

2026-01-21T08:41:57+00:00

In preparation to support FRL mode, move the PHY lane output enablement from the TMDS specific configuration to the common *_post_enable_lane() helper and make sure it gets turned off in *_phy_disable(). Signed-off-by: Cristian Ciocaltea Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-5-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Consistently use [rk_]hdptx_[tmds_] prefixes

2026-01-21T08:41:57+00:00

Fix the naming inconsistencies for some of the functions and global variables: * Add the missing 'rk_hdptx_' prefix to ropll_tmds_cfg variable * Replace '_ropll_tmds_' with '_tmds_ropll_' globally * Replace 'hdtpx' with 'hdptx' globally Signed-off-by: Cristian Ciocaltea Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-4-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul

phy: rockchip: samsung-hdptx: Fix coding style alignment

2026-01-21T08:41:57+00:00

Handle a bunch of reported checkpatch.pl complaints: CHECK: Alignment should match open parenthesis Signed-off-by: Cristian Ciocaltea Reviewed-by: Neil Armstrong Link: https://patch.msgid.link/20260113-phy-hdptx-frl-v6-3-8d5f97419c0b@collabora.com Signed-off-by: Vinod Koul