kernel/linux.git/drivers/phy/qualcomm, branch v7.2-rc1

Merge tag 'phy-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2026-06-23T22:41:48+00:00

Pull phy updates from Vinod Koul: "Bunch of new driver, device support in existing drivers/binding and few updates to existing drivers New Support: - Qualcomm Eliza QMP PHY, Eliza Synopsys eUSB2 support, Eliza PCIe phy support, Nord QMP UFS PHY, IPQ5210 USB3 PHY support - Econet EN751221 and EN7528 PCIe phy support - NXPs TJA1145 CAN transceiver phy support - TI DS125DF111 retimer phy support - Rockchip RK3528 usb phy support - TI J722S phy support - Axiado eMMC PHY driver - EyeQ5 Ethernet PHY driver - Generic PHY driver for Lynx 10G SerDes - Spacemit K3 USB2 PHY support Updates: - Tomi helping maintian zynqmp phys - lynx phy updates to support 25GBASER - Rockchip GRF for RK3568/RV1108 support - Qualcomm QSERDES COM v2 support" * tag 'phy-for-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (87 commits) phy: rockchip: inno-usb2: Add missing clkout_ctl_phy kerneldoc phy: Move MODULE_DEVICE_TABLE next to the table itself phy: add basic support for NXPs TJA1145 CAN transceiver dt-bindings: phy: add support for NXPs TJA1145 CAN transceiver phy: freescale: phy-fsl-imx8qm-lvds-phy: Fix missing pm_runtime_disable() on probe error path dt-bindings: phy: qcom,qmp-usb: Add ipq5210 USB3 PHY dt-bindings: phy: qcom,qusb2: Document IPQ5210 compatible phy: freescale: phy-fsl-imx8qm-lvds-phy: Use synchronous PM runtime put in reset MAINTAINERS: expand Lynx 28G entry to cover Lynx 10G SerDes phy: lynx-10g: new driver dt-bindings: phy: lynx-10g: initial document phy: lynx-28g: improve phy_validate() procedure phy: lynx-28g: optimize read-modify-write operation phy: lynx-28g: add support for big endian register maps phy: lynx-28g: common probe() and remove() phy: lynx-28g: make lynx_28g_pll_read_configuration() callable per PLL phy: lynx-28g: move struct lynx_info definitions downwards phy: lynx-28g: provide default lynx_lane_supports_mode() implementation phy: lynx-28g: generalize protocol converter accessors phy: lynx-28g: common lynx_pll_get() ...

phy: qcom: qmp-pcie: Add QMP PCIe PHY support for Eliza

2026-06-11T06:58:38+00:00

Add QMP PCIe PHY support for the Eliza SoC. Introduce a new Gen3x1 PHY configuration with Eliza-specific initialization tables, and reuse the existing sm8550 Gen3x2 configuration for the Gen3x2 PHY instance. Also add the missing QPHY_PCIE_V6_PCS_PCIE_INT_AUX_CLK_CONFIG1 register definition to the PCIe V6 PCS header. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260608-eliza-v3-3-9bdeb7434b28@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: qmp-usbc: Fix out-of-bounds array access in dp swing config

2026-05-19T10:12:11+00:00

swing_tbl and pre_emphasis_tbl are 4x4 arrays (valid indices 0-3), but the boundary check uses "> 4" instead of ">= 4", allowing index 4 to cause an out-of-bounds access. Reported-by: Dan Carpenter Fixes: 81791c45c8e0 ("phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support") Signed-off-by: Xiangxu Yin Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260227-master-v1-1-8d91b9407fdb@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom: qmp-combo: Move pipe_clk on/off to common

2026-05-19T10:10:48+00:00

Keep the USB pipe clock working when the phy is in DP-only mode, because the dwc controller still needs it for USB 2.0 over the same Type-C port. Tested with the BenQ RD280UA monitor which has a downstream-facing port for data passthrough that's manually switchable between USB 2 and 3, corresponding to 4-lane and 2-lane DP respectively. Note: the suspend/resume callbacks were already gating the enable/disable of this clock only on init_count and not usb_init_count! Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Signed-off-by: Val Packett Link: https://patch.msgid.link/20260304190827.176988-1-val@packett.cool Signed-off-by: Vinod Koul

phy: qcom-usb-hs: use flexible array member

2026-05-14T15:50:28+00:00

Simplify allocation by removing kmalloc_array and just doing kzalloc. Signed-off-by: Rosen Penev Link: https://patch.msgid.link/20260315214930.4621-1-rosenp@gmail.com Signed-off-by: Vinod Koul

phy: qcom: m31-eusb2: Make USB repeater optional

2026-05-10T11:58:58+00:00

A repeater is not required for the PHY to function. On systems with multiple PHY instances connected to a multi-port controller, some PHYs may be unconnected. All PHYs must still probe successfully even without attached repeaters, otherwise the controller probe fails. So make it optional. Signed-off-by: Wesley Cheng [abel.vesa@oss.qualcomm.com: commit re-worded to reflect actual reason] Reviewed-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Signed-off-by: Abel Vesa Reviewed-by: Neil Armstrong Reviewed-by: Konrad Dybcio Link: https://patch.msgid.link/20260302-phy-qcom-m31-eusb2-make-repeater-optional-v2-1-dbf714c72056@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom-qmp-ufs: Fix kaanapali PHY PLL lock failure after SM8650 G4 fix

2026-05-10T11:45:34+00:00

Commit 81af9e40e2e4 ("phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4") moved QPHY_V6_PCS_UFS_PLL_CNTL register configuration from the shared sm8650_ufsphy_g5_pcs table to the SM8650-specific sm8650_ufsphy_pcs base table to fix Gear 4 operation on SM8650. However, this change inadvertently broke kaanapali and SM8750 SoCs which also rely on the shared sm8650_ufsphy_g5_pcs table for Gear 5 configuration but use their own sm8750_ufsphy_pcs base table. After the change, kaanapali PHYs are left without the required PLL_CNTL = 0x33 setting, causing the PHY PLL to remain at its hardware reset default value, preventing PLL lock and resulting in DME_LINKSTARTUP timeouts. Fix this by adding the missing QPHY_V6_PCS_UFS_PLL_CNTL = 0x33 entry to the sm8750_ufsphy_pcs table, mirroring what the original commit already did for sm8650_ufsphy_pcs. Cc: stable@vger.kernel.org # v6.19.12 Fixes: 81af9e40e2e4 ("phy: qcom: qmp-ufs: Fix SM8650 PCS table for Gear 4") Signed-off-by: Nitin Rawat Reviewed-by: Abel Vesa Reviewed-by: Konrad Dybcio Reviewed-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260415104851.2763238-1-nitin.rawat@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom-qmp: Make QSERDES TXRX v2 registers explicit

2026-05-10T11:25:30+00:00

Rename QSERDES TXRX v2 registers and the header to make version explicit. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260314051325.198137-7-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom-qmp: Drop unused register headers

2026-05-10T11:25:29+00:00

None of qcom-qmp drivers uses header qserdes-com or qserdes-txrx-v2. Drop them. Signed-off-by: Shawn Guo Reviewed-by: Dmitry Baryshkov Link: https://patch.msgid.link/20260314051325.198137-6-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: qcom-qmp-usbc: Rename QCS615 DP PHY variables and functions

2026-05-10T11:25:29+00:00

Commit 81791c45c8e0 ("phy: qcom: qmp-usbc: Add QCS615 USB/DP PHY config and DP mode support") chose to name QCS615 DP PHY variables/functions with qmp_v2 prefix, by assuming that QMP PHY registers are versioned as a whole. However, the reality is that the registers are versioned in sub-modules like QSERDES COM and QSERDES TXRX respectively, e.g. QCS615 DP PHY has registers of QSERDES COM v2 and QSERDES TXRX v3. Thus it may cause confusion that qmp_v2_xxx table and functions access QSERDES TXRX v3 registers. Rename QCS615 DP PHY variables and functions to be prefixed by qcs615 instead of qmp_v2. This better aligns with how the driver names USB3 PHY variables for QCM2290 etc. Signed-off-by: Shawn Guo Link: https://patch.msgid.link/20260314051325.198137-5-shengchao.guo@oss.qualcomm.com Signed-off-by: Vinod Koul