kernel/linux.git/drivers/phy/qualcomm, branch v5.15.7

phy: qcom-snps: Correct the FSEL_MASK

2021-11-18T18:16:56+00:00

[ Upstream commit b475bf0ec40a2b13fb32ef62f5706576d5858460 ] The FSEL_MASK which selects the refclock is defined incorrectly. It should be [4:6] not [5:7]. Due to this incorrect definition, the BIT(7) in USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 is reset which keeps PHY analog blocks ON during suspend. Fix this issue by correctly defining the FSEL_MASK. Fixes: 51e8114f80d0 ("phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs") Signed-off-by: Sandeep Maheswaram Link: https://lore.kernel.org/r/1635135575-5668-1-git-send-email-quic_c_sanm@quicinc.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: qcom-qmp: another fix for the sc8180x PCIe definition

2021-11-18T18:16:56+00:00

[ Upstream commit 26f71abef580537d978f6299330689f029ee1e6c ] Commit f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") added SC8180X PCIe tables, but used sm8250_qmp_pcie_serdes_tbl as a serdes table because of the copy paste error. Commit bfccd9a71a08 ("phy: qcom-qmp: Fix sc8180x PCIe definition") corrected part of this mistake by pointing serdes_tbl to sc8180x_qmp_pcie_serdes_tbl, however the serdes_tbl_num field was not updated to use sc8180x table. So let's now fix the serdes_tbl_num field too. Fixes: bfccd9a71a08 ("phy: qcom-qmp: Fix sc8180x PCIe definition") Signed-off-by: Dmitry Baryshkov Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20211020155604.1374530-1-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: qcom-qusb2: Fix a memory leak on probe

2021-11-18T18:16:55+00:00

[ Upstream commit bf7ffcd0069d30e2e7ba2b827f08c89f471cd1f3 ] On success nvmem_cell_read() returns a pointer to a dynamically allocated buffer, and therefore it shall be freed after usage. The issue is reported by kmemleak: # cat /sys/kernel/debug/kmemleak unreferenced object 0xffff3b3803e4b280 (size 128): comm "kworker/u16:1", pid 107, jiffies 4294892861 (age 94.120s) hex dump (first 32 bytes): 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ backtrace: [<000000007739afdc>] __kmalloc+0x27c/0x41c [<0000000071c0fbf8>] nvmem_cell_read+0x40/0xe0 [<00000000e803ef1f>] qusb2_phy_init+0x258/0x5bc [<00000000fc81fcfa>] phy_init+0x70/0x110 [<00000000e3d48a57>] dwc3_core_soft_reset+0x4c/0x234 [<0000000027d1dbd4>] dwc3_core_init+0x68/0x990 [<000000001965faf9>] dwc3_probe+0x4f4/0x730 [<000000002f7617ca>] platform_probe+0x74/0xf0 [<00000000a2576cac>] really_probe+0xc4/0x470 [<00000000bc77f2c5>] __driver_probe_device+0x11c/0x190 [<00000000130db71f>] driver_probe_device+0x48/0x110 [<0000000019f36c2b>] __device_attach_driver+0xa4/0x140 [<00000000e5812ff7>] bus_for_each_drv+0x84/0xe0 [<00000000f4bac574>] __device_attach+0xe4/0x1c0 [<00000000d3beb631>] device_initial_probe+0x20/0x30 [<000000008019b9db>] bus_probe_device+0xa4/0xb0 Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Vladimir Zapolskiy Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210922233548.2150244-1-vladimir.zapolskiy@linaro.org Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: qcom-qmp: Add support for SM6115 UFS phy

2021-08-23T05:42:30+00:00

Add the tables and constants for init sequences for UFS QMP phy found in SM4250/6115 SoC. The phy is a variation of the v2 phy, but is mistakenly labeled as v3-660 in downstream sources. QSERDES COM, RX, TX registers match fully existing v2 registers, with a few additions. PCS registers don't have much in common, but there are no clashes with existing ones so new registers were added to existing v2 PCS pack. Signed-off-by: Iskren Chernev Link: https://lore.kernel.org/r/20210821155657.893165-3-iskren.chernev@gmail.com Signed-off-by: Vinod Koul

phy: qmp: Provide unique clock names for DP clocks

2021-08-20T03:52:30+00:00

The USB/DP combo PHY exposes the "qmp_dp_phy_pll_link_clk" and "qmp_dp_phy_pll_vco_div_clk" clocks, that are consumed by the display clock controller. But for boards with multiple enabled QMP USB/DP combo instances the hard coded names collides - and hence only the first probed device is allowed to register. Given that clocks are no longer reference globally by name and it's possible to replace the hard coded names by something unique, but still user friendly. The two new clock names are based on dev_name() and results in names such as "88ee000.phy::link_clk" and "88ee000.phy::vco_div_clk". Signed-off-by: Bjorn Andersson Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20210722030738.3385821-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp: add USB3 PHY support for IPQ6018

2021-08-06T13:04:58+00:00

Initialization is identical to the IPQ8074 USB3 PHY. Signed-off-by: Baruch Siach Link: https://lore.kernel.org/r/6eec7ef4ecd1e8360ebe8e425151121684e997ed.1628085910.git.baruch@tkos.co.il Signed-off-by: Vinod Koul

phy: qcom: qmp: Add SC8180x USB/DP combo

2021-08-06T12:06:55+00:00

The two USB QMPs are USB/DP compbo PHYs, add the compatible for this combination to allow DP output. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210721225630.3035861-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul

phy: qualcomm: phy-qcom-usb-hs: repair non-kernel-doc comment

2021-08-06T11:45:29+00:00

Fix errant use of "/**" to begin a comment although the comment is not kernel-doc notation. Just use "/*" instead. Fixes this kernel-doc warning: drivers/phy/qualcomm/phy-qcom-usb-hs.c:3: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * Copyright (C) 2016 Linaro Ltd Signed-off-by: Randy Dunlap Reported-by: kernel test robot Cc: Andy Gross Cc: Bjorn Andersson Cc: linux-arm-msm@vger.kernel.org Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20210723022548.25695-1-rdunlap@infradead.org Signed-off-by: Vinod Koul

phy: qcom-qmp: Fix sc8180x PCIe definition

2021-07-22T09:10:30+00:00

A copy paste error was snuck into the patch going upstream that made the SC8180x PCIe PHY use the SM8250 serdes table, but while this works there's some differences in the tables (and the SC8180x was left dangling). So correct the SC8180x definition to use the SC8180x serdes table. Fixes: f839f14e24f2 ("phy: qcom-qmp: Add sc8180x PCIe support") Reported-by: kernel test robot Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210721163029.2813497-1-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul

phy: qcom-qmp: Add sc8180x PCIe support

2021-07-20T10:34:39+00:00

The Qualcomm SC8180x platform has 4 PCIe controllers and PHYs, typically used to connect things such as a modem or NVME storage device. Add the programming sequence to get the PHYs up and running. Signed-off-by: Bjorn Andersson Link: https://lore.kernel.org/r/20210629004509.1788286-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul