kernel/linux.git/drivers/phy/qualcomm, branch v4.19.77

phy: ath79-usb: Fix the main reset name to match the DT binding

2019-03-05T16:58:48+00:00

[ Upstream commit 827cb0323928952c0db9515aba9d534fb1285b3f ] I submitted this driver several times before it got accepted. The first series hasn't been accepted but the DTS binding did made it. I then made a second series that added generic reset support to the PHY core, this in turn required a change to the DT binding. This second series seemed to have been ignored, so I did a third one without the change to the PHY core and the DT binding update, and this last attempt finally made it. But two months later the DT binding update from the second series has been integrated too. So now the driver doesn't match the binding and the only DTS using it. This patch fix the driver to match the new binding. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: ath79-usb: Fix the power on error path

2019-03-05T16:58:48+00:00

[ Upstream commit 009808154c69c48d5b41fc8cf5ad5ab5704efd8f ] In the power on function the error path doesn't return the suspend override to its proper state. It should should deassert this reset line to enable the suspend override. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845

2018-12-17T08:24:34+00:00

[ Upstream commit c88520db18ba0b9a41326c3b8680e7c09eb4c381 ] Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: qcom-qusb2: Use HSTX_TRIM fused value as is

2018-12-17T08:24:33+00:00

[ Upstream commit 6e34d358b24ffc40764eb3681164c79091765429 ] Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: qcom-usb-hs: Mark expected switch fall-through

2018-07-10T08:15:11+00:00

In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Signed-off-by: Gustavo A. R. Silva Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845

2018-05-20T16:21:33+00:00

There are two QUSB2 PHYs present on sdm845. In order to improve eye diagram for both the PHYs some parameters need to be changed. Provide device tree properties to override these from board specific device tree files. Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845

2018-05-20T16:21:30+00:00

QMP V3 UNI PHY is a single lane USB3 PHY without support for DisplayPort (DP). Main difference from DP combo QMPv3 PHY is that UNI PHY doesn't have dual RX/TX lanes and no separate DP_COM block for configuration related to type-c or DP. Also remove "qcom,qmp-v3-usb3-phy" compatible string which was earlier added for sdm845 only as there wouldn't be any user of same. While at it, fix has_pwrdn_delay attribute for USB-DP PHY configuration and. Reviewed-by: Evan Green Signed-off-by: Manu Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Fix crash if nvmem cell not specified

2018-05-20T16:21:27+00:00

Driver currently crashes due to NULL pointer deference while updating PHY tune register if nvmem cell is NULL. Since, fused value for Tune1/2 register is optional, we'd rather bail out. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Reviewed-by: Vivek Gautam Reviewed-by: Evan Green Cc: stable # 4.14+ Signed-off-by: Manu Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qmp: Enable pipe_clk before PHY initialization

2018-05-20T16:21:27+00:00

QMP PHY for USB/PCIE requires pipe_clk for locking of retime buffers at the pipe interface. Driver checks for PHY_STATUS without enabling pipe_clk due to which phy_init() fails with initialization timeout. Though pipe_clk is output from PHY (after PLL is programmed during initialization sequence) to GCC clock_ctl and then fed back to PHY but for PHY_STATUS register to reflect successful initialization pipe_clk from GCC must be present. Since, clock driver now ignores status_check for pipe_clk on clk_enable/disable, driver can safely enable/disable pipe_clk from phy_init/exit. Signed-off-by: Manu Gautam Signed-off-by: Kishon Vijay Abraham I

phy: Add a driver for the ATH79 USB phy

2018-04-25T05:23:00+00:00

The ATH79 USB phy is very simple, it only have a reset. On some SoC a second reset is used to force the phy in suspend mode regardless of the USB controller status. This driver is added to the qualcom directory as atheros is now part of qualcom and newer SoC of this familly are marketed under the qualcom name. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I