<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/phy/qualcomm, branch v4.19.16</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v4.19.16</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v4.19.16'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2018-12-17T08:24:34+00:00</updated>
<entry>
<title>phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845</title>
<updated>2018-12-17T08:24:34+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-10-16T07:22:07+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4724b50f9e093cfa9bea7caa5f25f00755bcc568'/>
<id>urn:sha1:4724b50f9e093cfa9bea7caa5f25f00755bcc568</id>
<content type='text'>
[ Upstream commit c88520db18ba0b9a41326c3b8680e7c09eb4c381 ]

Tune1 register on sdm845 is used to update HSTX_TRIM with fused
setting. Enable same by specifying update_tune1_with_efuse flag
for sdm845, otherwise driver ends up programming tune2 register.

Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845")
Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Acked-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: qcom-qusb2: Use HSTX_TRIM fused value as is</title>
<updated>2018-12-17T08:24:33+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-10-16T07:22:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d801a3eff5541321abd235243c8237b34d05ddf5'/>
<id>urn:sha1:d801a3eff5541321abd235243c8237b34d05ddf5</id>
<content type='text'>
[ Upstream commit 6e34d358b24ffc40764eb3681164c79091765429 ]

Fix HSTX_TRIM tuning logic which instead of using fused value
as HSTX_TRIM, incorrectly performs bitwise OR operation with
existing default value.

Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Reviewed-by: Stephen Boyd &lt;swboyd@chromium.org&gt;
Acked-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>phy: qcom-usb-hs: Mark expected switch fall-through</title>
<updated>2018-07-10T08:15:11+00:00</updated>
<author>
<name>Gustavo A. R. Silva</name>
<email>gustavo@embeddedor.com</email>
</author>
<published>2018-07-05T15:00:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=01abdcc5288f3bf3ea65378a4717138508b9c574'/>
<id>urn:sha1:01abdcc5288f3bf3ea65378a4717138508b9c574</id>
<content type='text'>
In preparation to enabling -Wimplicit-fallthrough, mark switch cases
where we are expecting to fall through.

Signed-off-by: Gustavo A. R. Silva &lt;gustavo@embeddedor.com&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845</title>
<updated>2018-05-20T16:21:33+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-05-02T21:06:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ef17f6e212caeebcbbb5da9e147eb3739061f4a1'/>
<id>urn:sha1:ef17f6e212caeebcbbb5da9e147eb3739061f4a1</id>
<content type='text'>
There are two QUSB2 PHYs present on sdm845. In order
to improve eye diagram for both the PHYs some parameters
need to be changed. Provide device tree properties to
override these from board specific device tree files.

Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Reviewed-by: Douglas Anderson &lt;dianders@chromium.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: qcom-qmp: Add QMP V3 USB3 UNI PHY support for sdm845</title>
<updated>2018-05-20T16:21:30+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-05-02T21:06:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f6721e5c0bb4e8abde0c6ef59ffc16711525df8d'/>
<id>urn:sha1:f6721e5c0bb4e8abde0c6ef59ffc16711525df8d</id>
<content type='text'>
QMP V3 UNI PHY is a single lane USB3 PHY without support
for DisplayPort (DP).
Main difference from DP combo QMPv3 PHY is that UNI PHY
doesn't have dual RX/TX lanes and no separate DP_COM
block for configuration related to type-c or DP.
Also remove "qcom,qmp-v3-usb3-phy" compatible string which
was earlier added for sdm845 only as there wouldn't be
any user of same.
While at it, fix has_pwrdn_delay attribute for USB-DP
PHY configuration and.

Reviewed-by: Evan Green &lt;evgreen@chromium.org&gt;
Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: qcom-qusb2: Fix crash if nvmem cell not specified</title>
<updated>2018-05-20T16:21:27+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-05-02T21:06:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0b4555e776ba0712c6fafb98b226b21fd05d2427'/>
<id>urn:sha1:0b4555e776ba0712c6fafb98b226b21fd05d2427</id>
<content type='text'>
Driver currently crashes due to NULL pointer deference
while updating PHY tune register if nvmem cell is NULL.
Since, fused value for Tune1/2 register is optional,
we'd rather bail out.

Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips")
Reviewed-by: Vivek Gautam &lt;vivek.gautam@codeaurora.org&gt;
Reviewed-by: Evan Green &lt;evgreen@chromium.org&gt;
Cc: stable &lt;stable@vger.kernel.org&gt; # 4.14+
Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: qcom-qmp: Enable pipe_clk before PHY initialization</title>
<updated>2018-05-20T16:21:27+00:00</updated>
<author>
<name>Manu Gautam</name>
<email>mgautam@codeaurora.org</email>
</author>
<published>2018-05-02T21:06:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=fdf37e1a1f050c5f03fbede28cc1b48f3cc80705'/>
<id>urn:sha1:fdf37e1a1f050c5f03fbede28cc1b48f3cc80705</id>
<content type='text'>
QMP PHY for USB/PCIE requires pipe_clk for locking of
retime buffers at the pipe interface. Driver checks for
PHY_STATUS without enabling pipe_clk due to which
phy_init() fails with initialization timeout.
Though pipe_clk is output from PHY (after PLL is programmed
during initialization sequence) to GCC clock_ctl and then fed
back to PHY but for PHY_STATUS register to reflect successful
initialization pipe_clk from GCC must be present.
Since, clock driver now ignores status_check for pipe_clk on
clk_enable/disable, driver can safely enable/disable pipe_clk
from phy_init/exit.

Signed-off-by: Manu Gautam &lt;mgautam@codeaurora.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: Add a driver for the ATH79 USB phy</title>
<updated>2018-04-25T05:23:00+00:00</updated>
<author>
<name>Alban Bedel</name>
<email>albeu@free.fr</email>
</author>
<published>2018-03-24T22:38:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=cd3bf368aa7a352a577be7b9540c6b5b2681bf17'/>
<id>urn:sha1:cd3bf368aa7a352a577be7b9540c6b5b2681bf17</id>
<content type='text'>
The ATH79 USB phy is very simple, it only have a reset. On some SoC a
second reset is used to force the phy in suspend mode regardless of the
USB controller status.

This driver is added to the qualcom directory as atheros is now part
of qualcom and newer SoC of this familly are marketed under the
qualcom name.

Signed-off-by: Alban Bedel &lt;albeu@free.fr&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'phy-for-4.17' of git://git.kernel.org/pub/scm/linux/kernel/git/kishon/linux-phy into usb-next</title>
<updated>2018-03-20T09:10:46+00:00</updated>
<author>
<name>Greg Kroah-Hartman</name>
<email>gregkh@linuxfoundation.org</email>
</author>
<published>2018-03-20T09:10:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=85a09bf492333300ca0a09199bce4cf1a5bdd5cb'/>
<id>urn:sha1:85a09bf492333300ca0a09199bce4cf1a5bdd5cb</id>
<content type='text'>
Kishon writes:

phy: for 4.17

 *) Add USB PHY driver for MDM6600 on Droid
 *) Add USB PHY driver for STM32 USB PHY Controller
 *) Add inno-usb2-phy driver for hi3798cv200 SoC
 *) Add combo phy driver (SATA/USB/PCIE) for HiSilicon STB SoCs
 *) Add USB3 PHY driver for Meson GXL and GXM
 *) Add support for R8A77965 Gen3 USB 2.0 PHY in phy-rcar-gen3-usb2 driver
 *) Add support for qualcomm QUSB2 V2 and QMP V3 USB3 PHY in phy-qcom-qusb2
    and phy-qcom-qmp PHY driver respectively
 *) Add support for runtime PM in phy-qcom-qusb2 and phy-qcom-qmp PHY drivers
 *) Add support for Allwinner R40 USB PHY in sun4i-usb PHY driver
 *) Add support in rockchip-typec PHY driver to make extcon optional and
    fallback to working in host mode if extcon is missing
 *) Add support in rockchip-typec PHY driver to mux PHYs connected to DP
 *) Add support to configure slew rate parameters in phy-mtk-tphy PHY driver
 *) Add workaround for missing Vbus det interrupts on Allwinner A23/A33
 *) Add USB speed related PHY modes in phy core
 *) Fix PHY 'structure' documentation
 *) Force rockchip-typec PHY to USB2 if DP-only mode is used
 *) Fix phy-qcom-qusb2 and phy-qcom-qmp PHY drivers to follow PHY reset and
    initialization sequence as per hardware programming manual
 *) Fix Marvell BG2CD SoC USB failure in phy-berlin-usb driver
 *) Minor fixes in lpc18xx-usb-otg, xusb-tegra210 and phy-rockchip-emmc PHY
    drivers

Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
<entry>
<title>phy: qcom-ufs: add MODULE_LICENSE tag</title>
<updated>2018-03-12T09:41:59+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2018-01-10T16:35:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=59fba0869acae06ff594dd7e9808ed673f53538a'/>
<id>urn:sha1:59fba0869acae06ff594dd7e9808ed673f53538a</id>
<content type='text'>
While the specific UFS PHY drivers (14nm and 20nm) have a module
license, the common base module does not, leading to a Kbuild
failure:

WARNING: modpost: missing MODULE_LICENSE() in drivers/phy/qualcomm/phy-qcom-ufs.o
FATAL: modpost: GPL-incompatible module phy-qcom-ufs.ko uses GPL-only symbol 'clk_enable'

This adds a module description and license tag to fix the build.
I added both Yaniv and Vivek as authors here, as Yaniv sent the initial
submission, while Vivek did most of the work since.

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Acked-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Signed-off-by: Kishon Vijay Abraham I &lt;kishon@ti.com&gt;
</content>
</entry>
</feed>
