kernel/linux.git/drivers/phy/qualcomm, branch linux-4.20.y

phy: ath79-usb: Fix the main reset name to match the DT binding

2019-03-05T16:59:37+00:00

[ Upstream commit 827cb0323928952c0db9515aba9d534fb1285b3f ] I submitted this driver several times before it got accepted. The first series hasn't been accepted but the DTS binding did made it. I then made a second series that added generic reset support to the PHY core, this in turn required a change to the DT binding. This second series seemed to have been ignored, so I did a third one without the change to the PHY core and the DT binding update, and this last attempt finally made it. But two months later the DT binding update from the second series has been integrated too. So now the driver doesn't match the binding and the only DTS using it. This patch fix the driver to match the new binding. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: ath79-usb: Fix the power on error path

2019-03-05T16:59:37+00:00

[ Upstream commit 009808154c69c48d5b41fc8cf5ad5ab5704efd8f ] In the power on function the error path doesn't return the suspend override to its proper state. It should should deassert this reset line to enable the suspend override. Signed-off-by: Alban Bedel Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sasha Levin

phy: qcom-qusb2: Fix HSTX_TRIM tuning with fused value for SDM845

2018-11-21T07:43:58+00:00

Tune1 register on sdm845 is used to update HSTX_TRIM with fused setting. Enable same by specifying update_tune1_with_efuse flag for sdm845, otherwise driver ends up programming tune2 register. Fixes: ef17f6e212ca ("phy: qcom-qusb2: Add QUSB2 PHYs support for sdm845") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-qusb2: Use HSTX_TRIM fused value as is

2018-11-21T07:43:58+00:00

Fix HSTX_TRIM tuning logic which instead of using fused value as HSTX_TRIM, incorrectly performs bitwise OR operation with existing default value. Fixes: ca04d9d3e1b1 ("phy: qcom-qusb2: New driver for QUSB2 PHY on Qcom chips") Signed-off-by: Manu Gautam Reviewed-by: Douglas Anderson Reviewed-by: Stephen Boyd Acked-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as Broken

2018-09-26T07:39:38+00:00

Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

scsi/ufs: qcom: Remove ufs_qcom_phy_*() calls from host

2018-09-26T07:39:37+00:00

The host makes direct calls into phy using ufs_qcom_phy_*() APIs. These APIs are only defined for 20nm qcom-ufs-qmp phy which is not being used by any architecture as yet. Future architectures too are not going to use 20nm ufs phy. So remove these ufs_qcom_phy_*() calls from host to let further change declare the 20nm phy as broken. Also remove couple of stale enum defines for ufs phy. Signed-off-by: Vivek Gautam Acked-by: Martin K. Petersen Signed-off-by: Kishon Vijay Abraham I

phy: qcom-ufs: Remove stale methods that handle ref clk

2018-09-26T07:39:36+00:00

Remove ufs_qcom_phy_enable/(disable)_dev_ref_clk() that are not being used by any code. Signed-off-by: Vivek Gautam Reviewed-by: Bjorn Andersson Signed-off-by: Kishon Vijay Abraham I

phy: Add QMP phy based UFS phy support for sdm845

2018-09-25T10:40:14+00:00

Add UFS PHY support to make SDM845 UFS work with common PHY framework. Signed-off-by: Can Guo Reviewed-by: Evan Green Reviewed-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: General struct and field cleanup

2018-09-25T10:40:14+00:00

Move MSM8996 specific PHY vreg list struct name to a genernal one as it is used by all PHYs. Add a specific field to handle dual lane situation. Signed-off-by: Can Guo Reviewed-by: Evan Green Reviewed-by: Manu Gautam Reviewed-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I

phy: Update PHY power control sequence

2018-09-25T10:40:13+00:00

All PHYs should be powered on before register configuration starts. And only PCIe PHYs need an extra power control before deasserts reset state. Signed-off-by: Can Guo Reviewed-by: Manu Gautam Reviewed-by: Vivek Gautam Reviewed-by: Evan Green Signed-off-by: Kishon Vijay Abraham I