kernel/linux.git/drivers/phy/qualcomm/Makefile, branch v6.1.168

phy: qcom-qmp: switch to new split QMP PHY driver

2022-06-09T18:19:41+00:00

Use new split QMP PHY driver and remove all monolith phy-qcom-qmp driver. Acked-by: Bjorn Andersson Tested-by: Bjorn Andersson # UFS, PCIe and USB on SC8180X Signed-off-by: Dmitry Baryshkov Link: https://lore.kernel.org/r/20220607213203.2819885-13-dmitry.baryshkov@linaro.org Signed-off-by: Vinod Koul

phy: qcom: Introduce new eDP PHY driver

2021-11-23T05:10:17+00:00

Many recent Qualcomm platforms comes with native DP and eDP support. This consists of a controller in the MDSS and a QMP-like PHY. While similar to the well known QMP block, the eDP PHY only has TX lanes and the programming sequences are slightly different. Rather than continuing the trend of parameterize the QMP driver to pieces, this introduces the support as a new driver. The registration of link and pixel clocks are borrowed from the QMP driver. The non-DP link frequencies are omitted for now. The eDP PHY is very similar to the dedicated (non-USB) DP PHY, but only the prior is supported for now. Signed-off-by: Bjorn Andersson Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/20211103234410.1352424-2-bjorn.andersson@linaro.org Signed-off-by: Vinod Koul

phy: qualcomm: add qcom ipq806x dwc usb phy driver

2020-07-20T06:24:03+00:00

This has lost in the original push for the dwc3 qcom driver. This is needed for ipq806x SoC as without this the usb ports doesn't work at all. Signed-off-by: Andy Gross Signed-off-by: Ansuel Smith Tested-by: Jonathan McDowell Link: https://lore.kernel.org/r/20200717131635.11076-1-ansuelsmth@gmail.com Signed-off-by: Vinod Koul

phy: qcom: remove ufs qmp phy driver

2020-07-08T11:07:05+00:00

The UFS specific QMP PHY driver started off supporting the 14nm and 20nm hardware. With the 20nm support marked broken for a long time and the 14nm support added to the common QMP PHY, this driver has not been used in a while. So delete it Reviewed-by: Bjorn Andersson Link: https://lore.kernel.org/r/20200629145452.123035-1-vkoul@kernel.org Signed-off-by: Vinod Koul

phy: qcom-snps: Add SNPS USB PHY driver for QCOM based SOCs

2020-05-05T05:14:04+00:00

This adds the SNPS FemtoPHY V2 driver used in QCOM SOCs. There are potentially multiple instances of this UTMI PHY on the SOC, all which can utilize this driver. The V2 driver will have a different register map compared to V1. Signed-off-by: Wesley Cheng Reviewed-by: Philipp Zabel Reviewed-by: Manu Gautam Reviewed-by: Vinod Koul Reviewed-by: Stephen Boyd Link: https://lore.kernel.org/r/1588636467-23409-3-git-send-email-wcheng@codeaurora.org Signed-off-by: Vinod Koul

phy: add driver for Qualcomm IPQ40xx USB PHY

2020-05-04T07:37:29+00:00

Add a driver to setup the USB PHY-s on Qualcom m IPQ40xx series SoCs. The driver sets up HS and SS phys. Signed-off-by: John Crispin Signed-off-by: Robert Marko Cc: Luka Perkov Link: https://lore.kernel.org/r/20200503201823.531757-1-robert.marko@sartura.hr Signed-off-by: Vinod Koul

phy: qualcomm: usb: Add SuperSpeed PHY driver

2020-03-20T14:04:29+00:00

Controls Qualcomm's SS PHY 1.0.0 implemented on various SoCs on both the 20nm and 28nm process nodes. Based on Sriharsha Allenki's original code. [bod: Removed dependency on extcon. Switched to gpio-usb-conn to handle VBUS On/Off Switched to usb-role-switch to bind gpio-usb-conn to DWC3] Signed-off-by: Jorge Ramirez-Ortiz Cc: Jorge Ramirez-Ortiz Cc: Sriharsha Allenki's Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Reviewed-by: Philipp Zabel Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Signed-off-by: Kishon Vijay Abraham I

phy: qualcomm: Add Synopsys 28nm Hi-Speed USB PHY driver

2020-03-20T14:04:29+00:00

Adds Qualcomm 28nm Hi-Speed USB PHY driver support. This PHY is usually paired with Synopsys DWC3 USB controllers on Qualcomm SoCs. The PHY can come in two flavours femtoPHY or picoPHY. This commit adds support for the femtoPHY with the possibility of extending to the picoPHY with additional future commits. Both PHYs are on a 28 nanometer process node. [bod: Updated qcom_snps_hsphy_set_mode to match new method signature Added disjunct on mode > 0 Removed regulator_set_voltage() in favour of setting floor in dts Removed 'snps' and from driver name Extended commit log to mention femtoPHY and picoPHY for future reference.] Signed-off-by: Shawn Guo Cc: Andy Gross Cc: Bjorn Andersson Cc: Kishon Vijay Abraham I Cc: Philipp Zabel Cc: Jorge Ramirez-Ortiz Cc: linux-arm-msm@vger.kernel.org Cc: linux-kernel@vger.kernel.org Tested-by: Bjorn Andersson Signed-off-by: Bryan O'Donoghue Signed-off-by: Kishon Vijay Abraham I

phy: qcom: Add Qualcomm PCIe2 PHY driver

2019-05-31T14:11:13+00:00

The Qualcomm PCIe2 PHY is based on design from Synopsys and found in several different platforms where the QMP PHY isn't used. Reviewed-by: Niklas Cassel Signed-off-by: Bjorn Andersson Signed-off-by: Kishon Vijay Abraham I

phy: qcom-ufs: Declare 20nm qcom ufs qmp phy as Broken

2018-09-26T07:39:38+00:00

Fork out separate configs for 14nm and 20nm qcom ufs qmp phys to declare the 20nm phy as broken. Signed-off-by: Vivek Gautam Signed-off-by: Kishon Vijay Abraham I