kernel/linux.git/drivers/phy/marvell, branch v7.1-rc5

phy: marvell: mvebu-a3700-utmi: fix incorrect USB2_PHY_CTRL register access

2026-05-10T11:21:35+00:00

The mvebu_a3700_utmi_phy_power_off() function tries to modify the USB2_PHY_CTRL register by using the IO address of the PHY IP block along with the readl/writel IO accessors. However, the register exist in the USB miscellaneous register space, and as such it must be accessed via regmap like it is done in the mvebu_a3700_utmi_phy_power_on() function. Change the code to use regmap_update_bits() for modífying the register to fix this. Fixes: cc8b7a0ae866 ("phy: add A3700 UTMI PHY driver") Signed-off-by: Gabor Juhos Reviewed-by: Miquel Raynal Link: https://patch.msgid.link/20260321-a3700-utmi-fix-usb2_phy_ctrl-access-v1-1-6005ff4b5058@gmail.com Signed-off-by: Vinod Koul

phy: marvell: mmp3-hsic: Avoid re-casting __iomem

2026-02-27T14:33:38+00:00

__iomem annotated memory must be accessed via dedicated accessors, even if actual code is correct (accessing the driver data in mmp3_hsic_phy_init() brings back the __iomem cast), but dropping its cast (with or without __force) when storing as driver data seems like less readable code for any future changes. Instead, add a dedicated wrapping structure just to hold the pointer without changing the __iomem cast. This makes the code explicit, obvious and solves the sparse warning: phy-mmp3-hsic.c:58:31: warning: cast removes address space '__iomem' of expression Signed-off-by: Krzysztof Kozlowski Link: https://patch.msgid.link/20260216110413.159994-5-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Vinod Koul

phy: mvebu-cp110-utmi: fix dr_mode property read from dts

2026-01-21T07:56:59+00:00

The problem with the current implementation is that it does not consider that the USB controller can have multiple PHY handles with different arguments count, as for example we have in our cn9131 based platform: "phys = <&cp0_comphy1 0>, <&cp0_utmi0>;". In such case calling "of_usb_get_dr_mode_by_phy" with -1 (no phy-cells) leads to not proper phy detection, taking the "marvell,cp110-utmi-phy" dts definition we can call the "of_usb_get_dr_mode_by_phy" with 0 (#phy-cells = <0>) and safely look for that phy. Signed-off-by: Aleksandar Gerasimovski Link: https://patch.msgid.link/20260106150643.922110-1-aleksandar.gerasimovski@belden.com Signed-off-by: Vinod Koul

phy: drop probe registration printks

2025-06-16T17:24:21+00:00

Drivers should generally be quiet on successful probe, but this is not followed by some PHY drivers, for example: snps-eusb2-hsphy 88e1000.phy: Registered Snps-eUSB2 phy qcom-eusb2-repeater c432000.spmi:pmic@7:phy@fd00: Registered Qcom-eUSB2 repeater qcom-eusb2-repeater c432000.spmi:pmic@a:phy@fd00: Registered Qcom-eUSB2 repeater qcom-eusb2-repeater c432000.spmi:pmic@b:phy@fd00: Registered Qcom-eUSB2 repeater snps-eusb2-hsphy fd3000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy fd9000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy fde000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy 88e0000.phy: Registered Snps-eUSB2 phy snps-eusb2-hsphy 88e2000.phy: Registered Snps-eUSB2 phy Drop (or demote to debug level) unnecessary registration info messages to make boot logs a little less noisy. Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20250523085112.11287-1-johan+linaro@kernel.org Signed-off-by: Vinod Koul

phy: marvell: Do not enable by default during compile testing

2025-04-11T07:18:34+00:00

Enabling the compile test should not cause automatic enabling of all drivers. Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250404121326.318936-1-krzysztof.kozlowski@linaro.org Signed-off-by: Vinod Koul

phy: marvell: Fix spelling mistake "exlicitly" -> "explicitly"

2024-12-04T14:11:59+00:00

Fix spelling mistake in mvebu_comphy_ethernet_init_reset comments. Signed-off-by: Advait Dhamorikar Link: https://lore.kernel.org/r/20241127104333.18944-1-advaitdhamorikar@gmail.com Signed-off-by: Vinod Koul

phy: mvebu-cp110-utmi: support swapping d+/d- lanes by dts property

2024-10-07T06:30:19+00:00

CP11x UTMI PHY supports swapping D+/D- signals via digital control register 1. Add support for the "swap-dx-lanes" device-tree property, which lists the port-ids that should swap D+ and D-. The property is evaluated in probe and applied before power-on during mvebu_cp110_utmi_port_setup. Signed-off-by: Josua Mayer Link: https://lore.kernel.org/r/20241002-mvebu-utmi-phy-v4-1-83783dc89b9d@solid-run.com Signed-off-by: Vinod Koul

phy: marvell: phy-mvebu-cp110-comphy: improve eth_port1 on comphy4

2024-08-04T17:22:11+00:00

According to the CN9100_MPP_information document, CP_SRD4 (comphy 4) supports 2500 BASE-X and 5000 BASE-R for ETH_PORT1. I was able to test that 2500 BASE-X is indeed supported. Unfortunately, our HW does not support 5000 BASE-R, but I assume from the document that it does, so I set the muxing there too to 0x1. Signed-off-by: Stefan Eichenberger Link: https://lore.kernel.org/r/20240711131612.98952-1-eichest@gmail.com Signed-off-by: Vinod Koul

phy: marvell: a3700-comphy: Fix hardcoded array size

2024-04-05T17:02:00+00:00

Replace hardcoded 'gbe_phy_init' array size by explicit one. Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation") Signed-off-by: Mikhail Kobuk Link: https://lore.kernel.org/r/20240321164734.49273-2-m.kobuk@ispras.ru Signed-off-by: Vinod Koul

phy: marvell: a3700-comphy: Fix out of bounds read

2024-04-05T17:02:00+00:00

There is an out of bounds read access of 'gbe_phy_init_fix[fix_idx].addr' every iteration after 'fix_idx' reaches 'ARRAY_SIZE(gbe_phy_init_fix)'. Make sure 'gbe_phy_init[addr]' is used when all elements of 'gbe_phy_init_fix' array are handled. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 934337080c6c ("phy: marvell: phy-mvebu-a3700-comphy: Add native kernel implementation") Signed-off-by: Mikhail Kobuk Reviewed-by: Miquel Raynal Link: https://lore.kernel.org/r/20240321164734.49273-1-m.kobuk@ispras.ru Signed-off-by: Vinod Koul