kernel/linux.git/drivers/phy/freescale, branch v6.1.124

phy: freescale: imx8m-pcie: fix pcie link-up instability

2024-05-02T14:29:31+00:00

[ Upstream commit 3a161017f1de55cc48be81f6156004c151f32677 ] Leaving AUX_PLL_REFCLK_SEL at its reset default of AUX_IN (PLL clock) proves to be more stable on the i.MX 8M Mini. Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Signed-off-by: Marcel Ziswiler Reviewed-by: Richard Zhu Link: https://lore.kernel.org/r/20240322130646.1016630-2-marcel@ziswiler.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: freescale: imx8m-pcie: Refine i.MX8MM PCIe PHY driver

2024-05-02T14:29:31+00:00

[ Upstream commit ca679c49c4463595499a053ba94328acb574fffa ] To make it more flexible and easy to expand. Refine i.MX8MM PCIe PHY driver. - Use gpr compatible string to avoid the codes duplications when add another platform PCIe PHY support. - Re-arrange the codes to let it more flexible and easy to expand. No functional change. Re-arrange the TX tuning, since internal registers can be wrote through APB interface before assertion of CMN_RST. Signed-off-by: Richard Zhu Signed-off-by: Lucas Stach Tested-by: Marek Vasut Tested-by: Richard Leitner Tested-by: Alexander Stein Reviewed-by: Lucas Stach Reviewed-by: Ahmad Fatoum Link: https://lore.kernel.org/r/1665625622-20551-4-git-send-email-hongxing.zhu@nxp.com Signed-off-by: Vinod Koul Stable-dep-of: 3a161017f1de ("phy: freescale: imx8m-pcie: fix pcie link-up instability") Signed-off-by: Sasha Levin

phy: freescale: phy-fsl-imx8-mipi-dphy: Fix alias name to use dashes

2024-03-06T14:45:19+00:00

[ Upstream commit 7936378cb6d87073163130e1e1fc1e5f76a597cf ] Devicetree spec lists only dashes as valid characters for alias names. Table 3.2: Valid characters for alias names, Devicee Specification, Release v0.4 Signed-off-by: Alexander Stein Fixes: 3fbae284887de ("phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support") Link: https://lore.kernel.org/r/20240110093343.468810-1-alexander.stein@ew.tq-group.com Signed-off-by: Vinod Koul Signed-off-by: Sasha Levin

phy: lynx-28g: serialize concurrent phy_set_mode_ext() calls to shared registers

2023-10-19T21:08:52+00:00

[ Upstream commit 139ad1143151a07be93bf741d4ea7c89e59f89ce ] The protocol converter configuration registers PCC8, PCCC, PCCD (implemented by the driver), as well as others, control protocol converters from multiple lanes (each represented as a different struct phy). So, if there are simultaneous calls to phy_set_mode_ext() to lanes sharing the same PCC register (either for the "old" or for the "new" protocol), corruption of the values programmed to hardware is possible, because lynx_28g_rmw() has no locking. Add a spinlock in the struct lynx_28g_priv shared by all lanes, and take the global spinlock from the phy_ops :: set_mode() implementation. There are no other callers which modify PCC registers. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller Signed-off-by: Sasha Levin

phy: lynx-28g: lock PHY while performing CDR lock workaround

2023-10-19T21:08:52+00:00

[ Upstream commit 0ac87fe54a171d18c5fb5345e3ee8d14e1b06f4b ] lynx_28g_cdr_lock_check() runs once per second in a workqueue to reset the lane receiver if the CDR has not locked onto bit transitions in the RX stream. But the PHY consumer may do stuff with the PHY simultaneously, and that isn't okay. Block concurrent generic PHY calls by holding the PHY mutex from this workqueue. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller Signed-off-by: Sasha Levin

phy: lynx-28g: cancel the CDR check work item on the remove path

2023-10-19T21:08:52+00:00

[ Upstream commit f200bab3756fe81493a1b280180dafa1d9ccdcf7 ] The blamed commit added the CDR check work item but didn't cancel it on the remove path. Fix this by adding a remove function which takes care of it. Fixes: 8f73b37cf3fb ("phy: add support for the Layerscape SerDes 28G") Signed-off-by: Ioana Ciornei Signed-off-by: Vladimir Oltean Signed-off-by: David S. Miller Signed-off-by: Sasha Levin

phy: freescale: imx8m-pcie: Fix the wrong order of phy_init() and phy_power_on()

2022-10-03T08:34:46+00:00

Refer to phy_core driver, phy_init() must be called before phy_power_on(). Fix the wrong order of phy_init() and phy_power_on() here. Link: https://lore.kernel.org/r/1662344583-18874-1-git-send-email-hongxing.zhu@nxp.com Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standalone phy driver") Tested-by: Alexander Stein Signed-off-by: Richard Zhu Signed-off-by: Lorenzo Pieralisi Acked-by: Vinod Koul Acked-by: Lorenzo Pieralisi

phy: freescale: Add i.MX8qm Mixel LVDS PHY support

2022-07-08T05:13:20+00:00

Add Freescale i.MX8qm LVDS PHY support. The PHY IP is from Mixel, Inc. Signed-off-by: Liu Ying Link: https://lore.kernel.org/r/20220706034810.2352641-4-victor.liu@nxp.com Signed-off-by: Vinod Koul

phy: freescale: imx8m-pcie: Handle IMX8_PCIE_REFCLK_PAD_UNUSED

2022-04-20T09:15:55+00:00

The 'fsl,refclk-pad-mode' DT property used to select clock source for PCIe PHY can have either of three values, IMX8_PCIE_REFCLK_PAD_INPUT, IMX8_PCIE_REFCLK_PAD_OUTPUT, IMX8_PCIE_REFCLK_PAD_UNUSED. The first two options are handled correctly by the driver, the last one is not, this patch implements support for the last option. The IMX8_PCIE_REFCLK_PAD_INPUT means PCIE_RESREF is PHY clock input, the IMX8_PCIE_REFCLK_PAD_OUTPUT means PHY clock are sourced from SoC internal PLL and output to PCIE_RESREF external IO pin. The last IMX8_PCIE_REFCLK_PAD_UNUSED is a combination of previous two, PHY clock are sourced from SoC internal PLL and not output anywhere. Reviewed-by: Richard Zhu Signed-off-by: Marek Vasut Cc: Fabio Estevam Cc: Kishon Vijay Abraham I Cc: Marcel Ziswiler Cc: NXP Linux Team Cc: Peng Fan Cc: Richard Zhu Cc: Shawn Guo Cc: Vinod Koul Cc: linux-arm-kernel@lists.infradead.org To: linux-phy@lists.infradead.org Link: https://lore.kernel.org/r/20220413140710.10074-1-marex@denx.de Signed-off-by: Vinod Koul

phy: freescale: phy-fsl-imx8-mipi-dphy: Add i.MX8qxp LVDS PHY mode support

2022-04-20T07:29:50+00:00

i.MX8qxp SoC embeds a Mixel MIPI DPHY + LVDS PHY combo which supports either a MIPI DSI display or a LVDS display. The PHY mode is controlled by SCU firmware and the driver would call a SCU firmware function to configure the PHY mode. The single LVDS PHY has 4 data lanes to support a LVDS display. Also, with a master LVDS PHY and a slave LVDS PHY, they may work together to support a LVDS display with 8 data lanes(usually, dual LVDS link display). Note that this patch supports the LVDS PHY mode only for the i.MX8qxp Mixel combo PHY, i.e., the MIPI DPHY mode is yet to be supported, so for now error would be returned from ->set_mode() if MIPI DPHY mode is passed over to it for the combo PHY. Cc: Guido Günther Cc: Robert Chiras Cc: Kishon Vijay Abraham I Cc: Vinod Koul Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Reviewed-by: Guido Günther Signed-off-by: Liu Ying Link: https://lore.kernel.org/r/20220419010852.452169-6-victor.liu@nxp.com Signed-off-by: Vinod Koul