kernel/linux.git/drivers/phy/cadence, branch v5.6.17

phy: cadence: Sierra: add phy_reset hook

2020-01-14T05:20:19+00:00

Some platforms e.g. J721e need lane swap register to be programmed before reset is deasserted. This patch ensures that we propagate the phy_reset back to the reset controller driver. Signed-off-by: Roger Quadros Signed-off-by: Sekhar Nori Reviewed-by: Jyri Sarha Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: remove redundant initialization of pointer regmap

2020-01-14T05:20:19+00:00

The pointer regmap is being initialized with a value that is never read and it is being updated later with a new value from phy->regmap_common_cdb. The initialization is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Use correct dev pointer in cdns_sierra_phy_remove()

2020-01-08T07:28:06+00:00

commit 44d30d622821d3b ("phy: cadence: Add driver for Sierra PHY"), incorrectly used parent device pointer to get driver data. Fix it here. Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz

2020-01-08T07:28:06+00:00

Set cmn_refclk_dig_div/cmn_refclk1_dig_div frequency to 25MHz as specified in "Common Module Clock Configurations" of the Cadence Sierra 16FFC Multi-Protocol PHY PMA Specification. It is set to 25MHz since the only user of Cadence Sierra SERDES, TI J721E SoC provides input clock frequency of 100MHz. For other frequencies, cmn_refclk_dig_div/cmn_refclk1_dig_div should be configured based on the "Common Module Clock Configurations". Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Change MAX_LANES of Sierra to 16

2020-01-08T07:28:06+00:00

Sierra SERDES IP supports upto 16 lanes (though not all of it will be enabled in a platform). Allow Sierra driver to support a maximum of upto 16 lanes. Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Check for PLL lock during PHY power on

2020-01-08T07:28:06+00:00

Check for PLL lock during PHY power on. Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Get reset control "array" for each link

2020-01-08T07:28:06+00:00

A link may have multiple lanes each with a separate reset. Get reset control "array" in order to reset all the lanes associated with the link. Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Configure both lane cdb and common cdb registers for external SSC

2020-01-08T07:28:06+00:00

The existing configuration done in Cadence Sierra driver is only for reference and is not used in any platforms. Remove them and configure both lane cdb and common cdb registers to be used with external SSC configuration. This is validated in TI J721E platform. Signed-off-by: Anil Varughese Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Modify register macro names to be in sync with Sierra user guide

2020-01-08T07:28:06+00:00

No functional change. Modify register offset macro names to be in sync with Sierra user guide. Signed-off-by: Kishon Vijay Abraham I

phy: cadence: Sierra: Make cdns_sierra_phy_init() as phy_ops

2020-01-08T07:28:06+00:00

Instead of invoking cdns_sierra_phy_init() from probe, add it in phy_ops so that it's initialized when the PHY consumer invokes phy_init() Signed-off-by: Kishon Vijay Abraham I