kernel/linux.git/drivers/phy/cadence, branch v5.15.7

phy: cadence-torrent: Check PIPE mode PHY status to be ready for operation

2021-08-17T10:12:44+00:00

PIPE PHY status is used to communicate the completion of several PHY functions. Check if PHY is ready for operation while configured for PIPE mode during startup. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-10-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Add debug information for PHY configuration

2021-08-17T10:12:44+00:00

Add debug information in probe regarding PHY configuration parameters like single link or multilink protocol along with number of lanes used for each protocol link. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-9-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Add separate functions for reusable code

2021-08-17T10:12:44+00:00

Torrent PHY driver currently supports single link DP configuration. Prepare driver to support multilink DP configurations by adding separate functions for common initialization sequence. Signed-off-by: Swapnil Jakhade Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20210728145454.15945-8-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Add PHY configuration for DP with 100MHz ref clock

2021-08-17T10:12:44+00:00

Add PHY configuration registers for single link DP with 100MHz reference clock and NO_SSC. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-7-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Add PHY registers for DP in array format

2021-08-17T10:12:44+00:00

Add PHY registers for single link DP in array format to simplify code and to improve readability. This supports already supported frequencies for DP of 19.2MHz and 25MHz. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-6-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Configure PHY registers as a function of input reference clock rate

2021-08-17T10:12:43+00:00

Torrent PHY supports multiple serdes standards with different input reference clock frequencies. PHY register values differ based on the reference clock rate. Add PHY input reference clock frequency as a new dimension to select proper register configuration. No functional change is intended. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-5-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Add enum for supported input reference clock frequencies

2021-08-17T10:12:43+00:00

Torrent PHY supports different input reference clock frequencies. Register configurations will be different based on reference clock value. Prepare driver to support such multiple reference clock frequencies. Signed-off-by: Swapnil Jakhade Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20210728145454.15945-4-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Reorder few functions to remove function declarations

2021-08-17T10:12:43+00:00

Reorder some functions to avoid function declarations. No functional change. Signed-off-by: Swapnil Jakhade Link: https://lore.kernel.org/r/20210728145454.15945-3-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence-torrent: Remove use of CamelCase to fix checkpatch CHECK message

2021-08-17T10:12:43+00:00

Script checkpatch with --strict option gives message: CHECK: Avoid CamelCase: CHECK: Avoid CamelCase: Fix this by removing CamelCase usage. No functional change. Signed-off-by: Swapnil Jakhade Reviewed-by: Kishon Vijay Abraham I Link: https://lore.kernel.org/r/20210728145454.15945-2-sjakhade@cadence.com Signed-off-by: Vinod Koul

phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()

2021-05-31T08:20:05+00:00

Fix to return a negative error code from the error handling case instead of 0, as done elsewhere in this function. Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16") Reported-by: Hulk Robot Signed-off-by: Wang Wensheng Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com Signed-off-by: Vinod Koul