kernel/linux.git/drivers/phy/cadence, branch v5.10.257Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.10.2572025-12-06T21:08:13+00:00phy: cadence: cdns-dphy: Enable lower resolutions in dphy2025-12-06T21:08:13+00:00Harikrishna Shenoyh-shenoy@ti.com2025-08-07T05:20:02+00:00urn:sha1:2272d5757ce5d3fb416d9f2497b015678eb85c0d
[ Upstream commit 43bd2c44515f8ee5c019ce6e6583f5640387a41b ]
Enable support for data lane rates between 80-160 Mbps cdns dphy
as mentioned in TRM [0] by setting the pll_opdiv field to 16.
This change enables lower resolutions like 640x480 at 60Hz.
[0]: https://www.ti.com/lit/zip/spruil1
(Table 12-552. DPHY_TX_PLL_CTRL Register Field Descriptions)
Reviewed-by: Udit Kumar <u-kumar1@ti.com>
Reviewed-by: Devarsh Thakkar <devarsht@ti.com>
Signed-off-by: Harikrishna Shenoy <h-shenoy@ti.com>
Link: https://lore.kernel.org/r/20250807052002.717807-1-h-shenoy@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
phy: cadence: Sierra: Fix error return code in cdns_sierra_phy_probe()2021-06-16T10:01:45+00:00Wang Wenshengwangwensheng4@huawei.com2021-05-17T01:57:49+00:00urn:sha1:d83075c25a28e6e8f02e531c8dd4b4e0b58c3ef5
commit 6411e386db0a477217607015e7d2910d02f75426 upstream.
Fix to return a negative error code from the error handling
case instead of 0, as done elsewhere in this function.
Fixes: a43f72ae136a ("phy: cadence: Sierra: Change MAX_LANES of Sierra to 16")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Wang Wensheng <wangwensheng4@huawei.com>
Link: https://lore.kernel.org/r/20210517015749.127799-1-wangwensheng4@huawei.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
phy: cadence: Sierra: Fix PHY power_on sequence2021-05-14T07:49:58+00:00Kishon Vijay Abraham Ikishon@ti.com2021-03-19T12:41:16+00:00urn:sha1:be6566144cbdadd8b369846f622563a855ee9505
commit 5b4f5757f83be34d1428a1ffbb68d4a1966e9aae upstream.
Commit 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
de-asserts PHY_RESET even before the configurations are loaded in
phy_init(). However PHY_RESET should be de-asserted only after
all the configurations has been initialized, instead of de-asserting
in probe. Fix it here.
Fixes: 44d30d622821d ("phy: cadence: Add driver for Sierra PHY")
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
Cc: <stable@vger.kernel.org> # v5.4+
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Link: https://lore.kernel.org/r/20210319124128.13308-2-kishon@ti.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
phy: cadence-torrent: Fix error code in cdns_torrent_phy_probe()2021-03-04T10:38:11+00:00Dan Carpenterdan.carpenter@oracle.com2020-12-17T11:04:59+00:00urn:sha1:5a602158b885870e779ef702b9944cdf1498e85a
[ Upstream commit 266df28f9ac16b0dff553d78bc3fb1c084b96b9d ]
This error path should return -EINVAL, but currently it returns
success.
Fixes: d09945eacad0 ("phy: cadence-torrent: Check total lane count for all subnodes is within limit")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Link: https://lore.kernel.org/r/X9s7Wxq+b6ls0q7o@mwanda
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
phy: cadence-torrent: Add USB + SGMII/QSGMII multilink configuration2020-09-18T05:17:22+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:46+00:00urn:sha1:6fd428f7806000d4be141f2ab4b08e2c5e998f05
Add USB + SGMII/QSGMII multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-14-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PCIe + USB multilink configuration2020-09-18T05:17:22+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:45+00:00urn:sha1:4acea473f38865e6bc438c1a17ff8f136dc6a0c8
Add PCIe + USB Unique SSC multilink configuration sequences.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-13-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add single link USB register sequences2020-09-18T05:17:21+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:44+00:00urn:sha1:9855d84b6bb1969e45c90d8ed82235a868b99cb6
Add support for single link USB configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-12-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add single link SGMII/QSGMII register sequences2020-09-18T05:17:21+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:43+00:00urn:sha1:9f33b76a35999a20dcea634639b88cf9d486ec9e
Add support for single link SGMII/QSGMII configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-11-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Configure PHY_PLL_CFG as part of link_cmn_vals2020-09-18T05:17:21+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:42+00:00urn:sha1:d66a63666919e9bf27ed9b45c50d35b59c86108d
Include PHY_PLL_CFG as a first register value to configure in
link_cmn_vals array values.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-10-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
phy: cadence-torrent: Add PHY link configuration sequences for single link2020-09-18T05:17:20+00:00Swapnil Jakhadesjakhade@cadence.com2020-09-17T07:30:41+00:00urn:sha1:cd9aa94737477c9d7cd8595ebc3558b00403f093
Add support to configure link_cmn_vals and xcvr_diag_vals in case of single
link PHY configuration.
Signed-off-by: Swapnil Jakhade <sjakhade@cadence.com>
Link: https://lore.kernel.org/r/1600327846-9733-9-git-send-email-sjakhade@cadence.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>