kernel/linux.git/drivers/phy/Makefile, branch v6.6.132

Revert "phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY"

2023-12-03T06:33:08+00:00

commit 7a784bcdd7e54f0599da3b2360e472238412623e upstream. This reverts commit 134e6d25f6bd06071e5aac0a7eefcea6f7713955. The recently added Realtek PHY drivers depend on the new port status notification mechanism which was built on the deprecated USB PHY implementation and devicetree binding. Specifically, using these PHYs would require describing the very same PHY using both the generic "phy" property and the deprecated "usb-phy" property which is clearly wrong. We should not be building new functionality on top of the legacy USB PHY implementation even if it is currently stuck in some kind of transitional limbo. Revert the new Realtek PHY drivers for now so that the port status notification interface can be reverted and replaced. Fixes: 134e6d25f6bd ("phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY") Cc: stable@vger.kernel.org # 6.6 Cc: Stanley Chang Signed-off-by: Johan Hovold Link: https://lore.kernel.org/r/20231106110654.31090-3-johan+linaro@kernel.org Signed-off-by: Greg Kroah-Hartman Signed-off-by: Greg Kroah-Hartman

Merge tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy

2023-09-03T17:38:02+00:00

Pull phy updates from Vinod Koul: "As usual a couple of new drivers, a bunch of new device support and few updates to existing drivers New Support: - Starfive dphy rx, JH7110 usb and pcie support - Rockchip rv1126 inno-dsi phy, rk3588 usb and pcie support - Qualcomm sa8775p PCIe support, M31 USB PHY driver - Samsung Exynos850 usb support Updates: - Mediatek dsi driver clock updates - Qualcomm sm8150 combo phy with reworking of qmp pcie driver - Xilinx zynqmp runtime PM support" * tag 'phy-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (83 commits) phy: exynos5-usbdrd: Add Exynos850 support phy: exynos5-usbdrd: Add 26MHz ref clk support phy: exynos5-usbdrd: Make it possible to pass custom phy ops dt-bindings: phy: samsung,usb3-drd-phy: Add Exynos850 support phy: qcom-qmp-combo: fix clock probing phy: qcom-qmp-pcie: support SM8150 PCIe QMP PHYs phy: qcom-qmp-pcie: populate offsets configuration phy: qcom-qmp-pcie: simplify clock handling phy: qcom-qmp-pcie: keep offset tables sorted phy: qcom-qmp-pcie: drop ln_shrd from v5_20 config dt-bindings: phy: qcom,qmp-pcie: describe SM8150 PCIe PHYs dt-bindings: phy: migrate QMP PCIe PHY bindings to qcom,sc8280xp-qmp-pcie-phy.yaml phy: fsl-imx8mq-usb: add dev_err_probe if getting vbus failed phy: qcom: Introduce M31 USB PHY driver dt-bindings: phy: qcom,m31: Document qcom,m31 USB phy phy: rockchip: inno-dsidphy: Add rv1126 support dt-bindings: phy: rockchip-inno-dsidphy: Document rv1126 dt-bindings: phy: mediatek,tphy: allow simple nodename pattern phy: amlogic: meson-g12a-usb2: fix Wvoid-pointer-to-enum-cast warning phy: marvell pxa-usb: fix Wvoid-pointer-to-enum-cast warning ...

phy: realtek: usb: Add driver for the Realtek SoC USB 2.0 PHY

2023-07-26T04:38:14+00:00

Realtek DHC (digital home center) RTD SoCs support DWC3 XHCI USB controller. Added the driver to drive the USB 2.0 PHY transceivers. Signed-off-by: Stanley Chang Link: https://lore.kernel.org/r/20230725033318.8361-2-stanley_chang@realtek.com Signed-off-by: Greg Kroah-Hartman

phy: starfive: Add JH7110 USB 2.0 PHY driver

2023-07-12T16:57:44+00:00

Add Starfive JH7110 SoC USB 2.0 PHY driver support. USB 2.0 PHY default connect to Cadence USB controller. Signed-off-by: Minda Chen Reviewed-by: Roger Quadros Link: https://lore.kernel.org/r/20230629075115.11934-4-minda.chen@starfivetech.com Signed-off-by: Vinod Koul

phy: usb: Add USB2.0 phy driver for Sunplus SP7021

2022-09-02T15:31:24+00:00

Add USB2.0 phy driver for Sunplus SP7021 Signed-off-by: Vincent Shih Link: https://lore.kernel.org/r/1658717052-26142-2-git-send-email-vincent.sunplus@gmail.com [vkoul: remove trailing line in driver file] Signed-off-by: Vinod Koul

phy: phy-can-transceiver: Add support for generic CAN transceiver driver

2021-06-14T05:50:17+00:00

The driver adds support for generic CAN transceivers. Currently the modes supported by this driver are standby and normal modes for TI TCAN1042 and TCAN1043 CAN transceivers. The transceiver is modelled as a phy with pins controlled by gpios, to put the transceiver in various device functional modes. It also gets the phy attribute max_link_rate for the usage of CAN drivers. Signed-off-by: Aswath Govindraju Acked-by: Marc Kleine-Budde Link: https://lore.kernel.org/r/20210510051006.11393-4-a-govindraju@ti.com Signed-off-by: Vinod Koul

phy: Add Sparx5 ethernet serdes PHY driver

2021-03-17T06:43:19+00:00

Add the Microchip Sparx5 ethernet serdes PHY driver for the 6G, 10G and 25G interfaces available in the Sparx5 SoC. Signed-off-by: Bjarni Jonasson Signed-off-by: Steen Hegelund Reviewed-by: Andrew Lunn Reviewed-by: Alexandre Belloni Link: https://lore.kernel.org/r/20210218161451.3489955-4-steen.hegelund@microchip.com Signed-off-by: Vinod Koul

PHY: Ingenic: Add USB PHY driver using generic PHY framework.

2020-12-05T08:09:30+00:00

Used the generic PHY framework API to create the PHY, this driver supoorts USB OTG PHY used in JZ4770 SoC, JZ4775 SoC, JZ4780 SoC, X1000 SoC, X1830 SoC and X2000 SoC. Co-developed-by: 漆鹏振 (Qi Pengzhen) Signed-off-by: 漆鹏振 (Qi Pengzhen) Signed-off-by: 周琰杰 (Zhou Yanjie) Tested-by: 周正 (Zhou Zheng) Tested-by: H. Nikolaus Schaller Reviewed-by: Paul Cercueil Link: https://lore.kernel.org/r/20201116141906.11758-4-zhouyanjie@wanyeetech.com Signed-off-by: Vinod Koul

phy: Add USB3 PHY support for Intel LGM SoC

2020-09-11T11:42:49+00:00

Add support for USB PHY on Intel LGM SoC. Signed-off-by: Ramuthevar Vadivel Murugan Reviewed-by: Philipp Zabel Link: https://lore.kernel.org/r/20200828022312.52724-3-vadivel.muruganx.ramuthevar@linux.intel.com Signed-off-by: Vinod Koul

phy: zynqmp: Add PHY driver for the Xilinx ZynqMP Gigabit Transceiver

2020-06-29T13:18:00+00:00

Xilinx ZynqMP SoCs have a Gigabit Transceiver with four lanes. All the high speed peripherals such as USB, SATA, PCIE, Display Port and Ethernet SGMII can rely on any of the four GT lanes for PHY layer. This patch adds driver for that ZynqMP GT core. Signed-off-by: Anurag Kumar Vulisha Signed-off-by: Laurent Pinchart Link: https://lore.kernel.org/r/20200629120054.29338-3-laurent.pinchart@ideasonboard.com Signed-off-by: Vinod Koul