<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/perf/Kconfig, branch v5.15.7</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.15.7</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.15.7'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2021-02-01T12:39:40+00:00</updated>
<entry>
<title>driver/perf: Remove ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3</title>
<updated>2021-02-01T12:39:40+00:00</updated>
<author>
<name>John Garry</name>
<email>john.garry@huawei.com</email>
</author>
<published>2021-02-01T10:24:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=34eb9359c111fd17ef8fb1ba671102438a7810c6'/>
<id>urn:sha1:34eb9359c111fd17ef8fb1ba671102438a7810c6</id>
<content type='text'>
The ARM_SMMU_V3_PMU dependency on ARM_SMMU_V3_PMU was added with the idea
that a SMMUv3 PMCG would only exist on a system with an associated SMMUv3.

However it is not the job of Kconfig to make these sorts of decisions (even
if it were true), so remove the dependency.

Signed-off-by: John Garry &lt;john.garry@huawei.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Link: https://lore.kernel.org/r/1612175042-56866-1-git-send-email-john.garry@huawei.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>driver/perf: Add PMU driver for the ARM DMC-620 memory controller</title>
<updated>2020-11-25T14:51:21+00:00</updated>
<author>
<name>Tuan Phan</name>
<email>tuanphan@os.amperecomputing.com</email>
</author>
<published>2020-11-04T19:30:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=53c218da220c3619b5befec4674ffa35d590092a'/>
<id>urn:sha1:53c218da220c3619b5befec4674ffa35d590092a</id>
<content type='text'>
DMC-620 PMU supports total 10 counters which each is
independently programmable to different events and can
be started and stopped individually.

Currently, it only supports ACPI. Other platforms feel free to test and add
support for device tree.

Usage example:
  #perf stat -e arm_dmc620_10008c000/clk_cycle_count/ -C 0
  Get perf event for clk_cycle_count counter.

  #perf stat -e arm_dmc620_10008c000/clkdiv2_allocate,mask=0x1f,match=0x2f,
  incr=2,invert=1/ -C 0
  The above example shows how to specify mask, match, incr,
  invert parameters for clkdiv2_allocate event.

Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Tuan Phan &lt;tuanphan@os.amperecomputing.com&gt;
Link: https://lore.kernel.org/r/1604518246-6198-1-git-send-email-tuanphan@os.amperecomputing.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>perf: Add Arm CMN-600 PMU driver</title>
<updated>2020-09-28T17:50:20+00:00</updated>
<author>
<name>Robin Murphy</name>
<email>robin.murphy@arm.com</email>
</author>
<published>2020-09-18T13:28:38+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0ba64770a2f2e5a104bf835e133d78d3f82287ad'/>
<id>urn:sha1:0ba64770a2f2e5a104bf835e133d78d3f82287ad</id>
<content type='text'>
Initial driver for PMU event counting on the Arm CMN-600 interconnect.
CMN sports an obnoxiously complex distributed PMU system as part of
its debug and trace features, which can do all manner of things like
sampling, cross-triggering and generating CoreSight trace. This driver
covers the PMU functionality, plus the relevant aspects of watchpoints
for simply counting matching flits.

Tested-by: Tsahi Zidenberg &lt;tsahee@amazon.com&gt;
Tested-by: Tuan Phan &lt;tuanphan@os.amperecomputing.com&gt;
Signed-off-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>soc: qcom: Separate kryo l2 accessors from PMU driver</title>
<updated>2020-07-11T00:08:55+00:00</updated>
<author>
<name>Ilia Lin</name>
<email>ilialin@codeaurora.org</email>
</author>
<published>2020-07-03T08:49:41+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6d0efeb14bbe2350a94ba07b403a686d731c5179'/>
<id>urn:sha1:6d0efeb14bbe2350a94ba07b403a686d731c5179</id>
<content type='text'>
The driver provides kernel level API for other drivers
to access the MSM8996 L2 cache registers.
Separating the L2 access code from the PMU driver and
making it public to allow other drivers use it.
The accesses must be separated with a single spinlock,
maintained in this driver.

Signed-off-by: Ilia Lin &lt;ilialin@codeaurora.org&gt;
Signed-off-by: Loic Poulain &lt;loic.poulain@linaro.org&gt;
Link: https://lore.kernel.org/r/1593766185-16346-2-git-send-email-loic.poulain@linaro.org
Acked-by: Will Deacon &lt;will@kernel.org&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>drivers/perf: hisi: Permit modular builds of HiSilicon uncore drivers</title>
<updated>2020-05-18T17:18:39+00:00</updated>
<author>
<name>Zhou Wang</name>
<email>wangzhou1@hisilicon.com</email>
</author>
<published>2020-05-07T02:58:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=97807325a02b41de2f641d98dda1041549a23cd8'/>
<id>urn:sha1:97807325a02b41de2f641d98dda1041549a23cd8</id>
<content type='text'>
This patch lets HiSilicon uncore PMU driver can be built as modules.
A common module and three specific uncore PMU driver modules will be built.

Export necessary functions in hisi_uncore_pmu module, and change
irq_set_affinity to irq_set_affinity_hint to pass compile.

Signed-off-by: Zhou Wang &lt;wangzhou1@hisilicon.com&gt;
Tested-by: Qi Liu &lt;liuqi115@huawei.com&gt;
Reviewed-by: Shaokun Zhang &lt;zhangshaokun@hisilicon.com&gt;
Link: https://lore.kernel.org/r/1588820305-174479-1-git-send-email-wangzhou1@hisilicon.com
Signed-off-by: Will Deacon &lt;will@kernel.org&gt;
</content>
</entry>
<entry>
<title>drivers/perf: imx_ddr: Add DDR performance counter support to perf</title>
<updated>2019-06-13T10:07:57+00:00</updated>
<author>
<name>Frank Li</name>
<email>frank.li@nxp.com</email>
</author>
<published>2019-05-01T18:43:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9a66d36cc7ace8062bd703d1edfb99437a2ddf2b'/>
<id>urn:sha1:9a66d36cc7ace8062bd703d1edfb99437a2ddf2b</id>
<content type='text'>
Add DDR performance monitor support for iMX8QXP. The PMU consists of 3
programmable event counters and a single dedicated cycle counter.

Example usage:

 $ perf stat -a -e \
   imx8_ddr0/read-cycles/,imx8_ddr0/write-cycles/,imx8_ddr0/precharge/ ls

- or -

 $ perf stat -a -e \
   imx8_ddr0/cycles/,imx8_ddr0/read-access/,imx8_ddr0/write-access/ ls

Other events are supported, and advertised via perf list.

Reviewed-by: Andrey Smirnov &lt;andrew.smirnov@gmail.com&gt;
Signed-off-by: Frank Li &lt;Frank.Li@nxp.com&gt;
[will: rewrote commit message/kconfig and used #defines for dev/cpuhp names]
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>treewide: Add SPDX license identifier - Makefile/Kconfig</title>
<updated>2019-05-21T08:50:46+00:00</updated>
<author>
<name>Thomas Gleixner</name>
<email>tglx@linutronix.de</email>
</author>
<published>2019-05-19T12:07:45+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1'/>
<id>urn:sha1:ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1</id>
<content type='text'>
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
</entry>
<entry>
<title>perf/smmuv3: Add arm64 smmuv3 pmu driver</title>
<updated>2019-04-04T15:49:21+00:00</updated>
<author>
<name>Neil Leeder</name>
<email>nleeder@codeaurora.org</email>
</author>
<published>2019-03-26T15:17:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=7d839b4b9e00645e49345d6ce5dfa8edf53c1a21'/>
<id>urn:sha1:7d839b4b9e00645e49345d6ce5dfa8edf53c1a21</id>
<content type='text'>
Adds a new driver to support the SMMUv3 PMU and add it into the
perf events framework.

Each SMMU node may have multiple PMUs associated with it, each of
which may support different events.

SMMUv3 PMCG devices are named as smmuv3_pmcg_&lt;phys_addr_page&gt; where
&lt;phys_addr_page&gt; is the physical page address of the SMMU PMCG
wrapped to 4K boundary. For example, the PMCG at 0xff88840000 is
named smmuv3_pmcg_ff88840

Filtering by stream id is done by specifying filtering parameters
with the event. options are:
   filter_enable    - 0 = no filtering, 1 = filtering enabled
   filter_span      - 0 = exact match, 1 = pattern match
   filter_stream_id - pattern to filter against

Example: perf stat -e smmuv3_pmcg_ff88840/transaction,filter_enable=1,
                       filter_span=1,filter_stream_id=0x42/ -a netperf

Applies filter pattern 0x42 to transaction events, which means events
matching stream ids 0x42 &amp; 0x43 are counted as only upper StreamID
bits are required to match the given filter. Further filtering
information is available in the SMMU documentation.

SMMU events are not attributable to a CPU, so task mode and sampling
are not supported.

Signed-off-by: Neil Leeder &lt;nleeder@codeaurora.org&gt;
Signed-off-by: Shameer Kolothum &lt;shameerali.kolothum.thodi@huawei.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
[will: fold in review feedback from Robin]
[will: rewrite Kconfig text and allow building as a module]
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>drivers/perf: Add Cavium ThunderX2 SoC UNCORE PMU driver</title>
<updated>2018-12-06T13:03:17+00:00</updated>
<author>
<name>Kulkarni, Ganapatrao</name>
<email>Ganapatrao.Kulkarni@cavium.com</email>
</author>
<published>2018-12-06T11:51:31+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=69c32972d59388c041268e8206e8eb1acff29b9a'/>
<id>urn:sha1:69c32972d59388c041268e8206e8eb1acff29b9a</id>
<content type='text'>
This patch adds a perf driver for the PMU UNCORE devices DDR4 Memory
Controller(DMC) and Level 3 Cache(L3C). Each PMU supports up to 4
counters. All counters lack overflow interrupt and are
sampled periodically.

Reviewed-by: Suzuki K Poulose &lt;suzuki.poulose@arm.com&gt;
Signed-off-by: Ganapatrao Kulkarni &lt;ganapatrao.kulkarni@cavium.com&gt;
[will: consistent enum cpuhp_state naming]
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
<entry>
<title>drivers/perf: Remove ARM_SPE_PMU explicit PERF_EVENTS dependency</title>
<updated>2018-05-22T16:11:12+00:00</updated>
<author>
<name>John Garry</name>
<email>john.garry@huawei.com</email>
</author>
<published>2018-05-22T15:54:04+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b89205bd508ed384253b4449c6a7a755b956a0f8'/>
<id>urn:sha1:b89205bd508ed384253b4449c6a7a755b956a0f8</id>
<content type='text'>
Since commit bddb9b68d3fb ("drivers/perf: commonise PERF_EVENTS
dependency"), all perf drivers depend on PERF_EVENTS config under a
common menu.

Config ARM_SPE_PMU still declares explicitly a dependency on
PERF_EVENTS, which is unneeded, so remove it.

Acked-by: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: John Garry &lt;john.garry@huawei.com&gt;
Signed-off-by: Will Deacon &lt;will.deacon@arm.com&gt;
</content>
</entry>
</feed>
