Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=linux-4.16.y 2018-01-26T17:45:16+00:00 2018-01-26T17:45:16+00:00 Bjorn Helgaas bhelgaas@google.com 2018-01-26T17:45:16+00:00 urn:sha1:7328c8f48d1895b3fec98b0b319cfb856b4c4fa1 b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") added SPDX GPL-2.0 to several PCI files that previously contained no license information. Add SPDX GPL-2.0 to all other PCI files that did not contain any license information and hence were under the default GPL version 2 license of the kernel. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 2017-10-05T20:52:55+00:00 Linus Walleij linus.walleij@linaro.org 2017-09-26T18:02:20+00:00 urn:sha1:68a15eb7bd0cf180eb214c79aa4e1662c5eeb97c This PCI host bridge from V3 Semiconductor needs no further introduction. An ancient driver for it has been sitting in arch/arm/mach-integrator/pci_v3.* since before v2.6.12 and the initial migration to git. But we need to get the drivers out of arch/arm/* and get proper handling of the old drivers, rewrite and clean up so the PCI maintainer can control the mass of drivers without having to run all over the kernel. We also switch swiftly to all the new infrastructure found in the PCI hosts as of late. Some code is preserved so I have added an extensive list of authors in the top comment section. This driver probes with the following result: OF: PCI: host bridge /pciv3@62000000 ranges: OF: PCI: No bus range found for /pciv3@62000000, using [bus 00-ff] OF: PCI: IO 0x60000000..0x6000ffff -> 0x00000000 OF: PCI: MEM 0x40000000..0x4fffffff -> 0x40000000 OF: PCI: MEM 0x50000000..0x5fffffff -> 0x50000000 pci-v3-semi 62000000.pciv3: initialized PCI V3 Integrator/AP integration pci-v3-semi 62000000.pciv3: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [bus 00-ff] pci_bus 0000:00: root bus resource [io 0x0000-0xffff] pci_bus 0000:00: root bus resource [mem 0x40000000-0x4fffffff] pci_bus 0000:00: root bus resource [mem 0x50000000-0x5fffffff pref] pci-v3-semi 62000000.pciv3: parity error interrupt pci-v3-semi 62000000.pciv3: master abort error interrupt pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt pci-v3-semi 62000000.pciv3: master abort error interrupt (repeats a few times) pci 0000:00:09.0: [1011:0024] type 01 class 0x060400 pci-v3-semi 62000000.pciv3: master abort error interrupt pci-v3-semi 62000000.pciv3: PCI target LB->PCI READ abort interrupt pci 0000:00:0b.0: [8086:1229] type 00 class 0x020000 pci 0000:00:0b.0: reg 0x10: [mem 0x00000000-0x00000fff pref] pci 0000:00:0b.0: reg 0x14: [io 0x0000-0x001f] pci 0000:00:0b.0: reg 0x18: [mem 0x00000000-0x000fffff] pci 0000:00:0b.0: reg 0x30: [mem 0x00000000-0x000fffff pref] pci 0000:00:0b.0: supports D1 D2 pci 0000:00:0b.0: PME# supported from D0 D1 D2 D3hot pci 0000:00:0c.0: [5333:8811] type 00 class 0x030000 pci 0000:00:0c.0: reg 0x10: [mem 0x00000000-0x03ffffff] pci 0000:00:0c.0: reg 0x30: [mem 0x00000000-0x0000ffff pref] pci 0000:00:0c.0: vgaarb: VGA device added: decodes=io+mem,owns=io,locks=none PCI: bus0: Fast back to back transfers disabled PCI: bus1: Fast back to back transfers enabled pci 0000:00:0c.0: BAR 0: assigned [mem 0x40000000-0x43ffffff] pci 0000:00:0b.0: BAR 2: assigned [mem 0x44000000-0x440fffff] pci 0000:00:0b.0: BAR 6: assigned [mem 0x50000000-0x500fffff pref] pci 0000:00:0c.0: BAR 6: assigned [mem 0x50100000-0x5010ffff pref] pci 0000:00:0b.0: BAR 0: assigned [mem 0x50110000-0x50110fff pref] pci 0000:00:0b.0: BAR 1: assigned [io 0x1000-0x101f] pci 0000:00:09.0: PCI bridge to [bus 01] pci 0000:00:0b.0: Firmware left e100 interrupts enabled; disabling (...) e100: Intel(R) PRO/100 Network Driver, 3.5.24-k2-NAPI e100: Copyright(c) 1999-2006 Intel Corporation e100 0000:00:0b.0: enabling device (0146 -> 0147) e100 0000:00:0b.0 eth0: addr 0x50110000, irq 31, MAC addr 00:08:c7:99:d2:57 > lspci 00:0b.0 Class 0200: 8086:1229 00:09.0 Class 0604: 1011:0024 00:0c.0 Class 0300: 5333:8811 > cat /proc/iomem 40000000-4fffffff : V3 PCI NON-PRE-MEM 40000000-43ffffff : 0000:00:0c.0 44000000-440fffff : 0000:00:0b.0 44000000-440fffff : e100 50000000-5fffffff : V3 PCI PRE-MEM 50000000-500fffff : 0000:00:0b.0 50100000-5010ffff : 0000:00:0c.0 50110000-50110fff : 0000:00:0b.0 50110000-50110fff : e100 61000000-61ffffff : /pciv3@62000000 62000000-6200ffff : /pciv3@62000000 Signed-off-by: Linus Walleij <linus.walleij@linaro.org> [bhelgaas: fold in %pR fixes from Arnd Bergmann <arnd@arndb.de>: http://lkml.kernel.org/r/20171011140224.3770968-1-arnd@arndb.de] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> 2017-09-07T18:24:11+00:00 Bjorn Helgaas bhelgaas@google.com 2017-09-07T18:24:11+00:00 urn:sha1:99fd1b958cd36dc13fa441d63c4e93a39e17fb65 * pci/host-xilinx: PCI: xilinx-nwl: Fix platform_get_irq() error handling PCI: xilinx: Allow build on MIPS platforms PCI: xilinx: Don't enable config completion interrupts PCI: xilinx: Unify INTx & MSI interrupt decode PCI: xilinx-nwl: Translate INTx range to hwirqs 0-3 PCI: xilinx: Translate INTx range to hwirqs 0-3 2017-08-30T13:23:57+00:00 Ryder Lee ryder.lee@mediatek.com 2017-08-10T06:34:59+00:00 urn:sha1:b099631df160ec608cd6147f4d20a8042567a5b8 MT2712 and MT7622 using a new IP block of Gen2 controller which has two root ports and shares the same probing flow with MT2701/MT7623. Both MT2712 and MT7622 have the same per-port control registers, but there are slight differences between them: - MT7622 has more clocks than MT2712. - MT7622 has shared control registers which are used to enable LTSSM and ASPM while MT2712 does not. Add host controller support for MT2712/MT7622. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> [bhelgaas: folded in fix from http://lkml.kernel.org/r/1502715868-17651-2-git-send-email-honghui.zhang@mediatek.com] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2017-08-16T16:44:37+00:00 Paul Burton paul.burton@imgtec.com 2017-08-15T21:25:29+00:00 urn:sha1:293962d678c08364981f19c0d0ea3f877888242f Allow the xilinx-pcie driver to be built on MIPS platforms which make use of generic PCI drivers rather than legacy MIPS-specific interfaces. This is used on the MIPS Boston development board. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Bharat Kumar Gogada <bharatku@xilinx.com> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Ravikiran Gummaluri <rgummal@xilinx.com> 2017-07-07T18:42:25+00:00 Bjorn Helgaas bhelgaas@google.com 2017-07-07T18:42:25+00:00 urn:sha1:6aed468480e8b03ece5a395fe8013e66348a2547 * pci/host-tango: PCI: tango: Add Sigma Designs Tango SMP8759 PCIe host bridge support PCI: Add DT binding for Sigma Designs Tango PCIe controller Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile 2017-07-07T18:41:28+00:00 Marc Gonzalez marc_gonzalez@sigmadesigns.com 2017-06-20T08:17:40+00:00 urn:sha1:5e14e9fac308daf5607362f879e6de67e0b8dd5b This driver is required to work around several hardware bugs in the PCIe controller. The SMP8759 does not support legacy interrupts or IO space. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> [bhelgaas: add CONFIG_BROKEN dependency, various cleanups] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2017-07-02T23:44:45+00:00 Ryder Lee ryder.lee@mediatek.com 2017-05-21T03:42:24+00:00 urn:sha1:637cfacae96fa6d4166866a7fd2f97af681e6e0d Add support for the MediaTek PCIe Gen2 controller which can be found on MT7623 series SoCs. [bhelgaas: fold in mtk_pcie_parse_and_add_res() bugfix from http://lkml.kernel.org/r/1496644078-27122-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in MAINTAINERS update from http://lkml.kernel.org/r/1497588789-28607-1-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in pci_scan_root_bus_bridge() update and leak fix from http://lkml.kernel.org/r/1498555451-55073-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in powerup fixes from http://lkml.kernel.org/r/1497866400-41844-2-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in poweroff when link down fixes from http://lkml.kernel.org/r/1497866400-41844-3-git-send-email-ryder.lee@mediatek.com] [bhelgaas: fold in optional property fixes from http://lkml.kernel.org/r/1497866400-41844-4-git-send-email-ryder.lee@mediatek.com] [bhelgaas: set host->map_irq and host->swizzle_irq and drop pci_fixup_irqs(), remove unnecessary "return", rename mtk_pcie_link_is_up() to mtk_pcie_link_up() for consistency, add local struct device pointer] [bhelgaas: fold in pci_add_flags() removal from http://lkml.kernel.org/r/1499061300-55951-1-git-send-email-ryder.lee@mediatek.com] Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> 2017-04-28T15:33:10+00:00 Bjorn Helgaas bhelgaas@google.com 2017-04-28T15:33:10+00:00 urn:sha1:95773672830d49ed6202bfa47cbb752823c96593 * pci/host-rockchip: PCI: rockchip: Modularize PCI: Export pci_remap_iospace() and pci_unmap_iospace() PCI: rockchip: Add remove() support PCI: rockchip: Set PCI_EXP_LNKSTA_SLC in the Root Port PCI: rockchip: Advertise 128-byte Read Completion Boundary support PCI: rockchip: Make 'return 0' more obvious in probe() PCI: rockchip: Unindent rockchip_pcie_set_power_limit() PCI: rockchip: Handle regulator_get_current_limit() failure correctly 2017-04-28T15:33:00+00:00 Bjorn Helgaas bhelgaas@google.com 2017-04-28T15:33:00+00:00 urn:sha1:24c53a66bd687a186f55f0845c08a6d073864798 * pci/host-iproc: PCI: iproc: Add PCI_DOMAIN dependency to PCI Kconfig