kernel/linux.git/drivers/pci/controller/plda, branch v6.12.80

PCI: Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS

2025-09-04T13:31:55+00:00

commit 817f989700fddefa56e5e443e7d138018ca6709d upstream. Rename PCIE_RESET_CONFIG_DEVICE_WAIT_MS to PCIE_RESET_CONFIG_WAIT_MS. Suggested-by: Bjorn Helgaas Signed-off-by: Niklas Cassel Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20250625102347.1205584-10-cassel@kernel.org Signed-off-by: Marek Vasut Signed-off-by: Greg Kroah-Hartman

PCI: microchip: Set inbound address translation for coherent or non-coherent mode

2025-02-08T08:57:56+00:00

[ Upstream commit 1390a33b3d04fdf6ba4e3e7082107a12027fc188 ] On Microchip PolarFire SoC the PCIe Root Port can be behind one of three general purpose Fabric Interface Controller (FIC) buses that encapsulates an AXI-S bus. Depending on which FIC(s) the Root Port is connected through to CPU space, and what address translation is done by that FIC, the Root Port driver's inbound address translation may vary. For all current supported designs and all future expected designs, inbound address translation done by a FIC on PolarFire SoC varies depending on whether PolarFire SoC is operating in coherent DMA mode or noncoherent DMA mode. The setup of the outbound address translation tables in the Root Port driver only needs to handle these two cases. Setup the inbound address translation tables to one of two address translations, depending on whether the Root Port is being used with coherent DMA or noncoherent DMA. Link: https://lore.kernel.org/r/20241011140043.1250030-3-daire.mcnamara@microchip.com Fixes: 6f15a9c9f941 ("PCI: microchip: Add Microchip PolarFire PCIe controller driver") Signed-off-by: Daire McNamara [bhelgaas: adapt for ac7f53b7e728 ("PCI: microchip: Add support for using either Root Port 1 or 2")] Signed-off-by: Bjorn Helgaas Acked-by: Conor Dooley Signed-off-by: Sasha Levin

PCI: microchip: Add support for using either Root Port 1 or 2

2025-02-08T08:57:56+00:00

[ Upstream commit ac7f53b7e7283fee35ad12de8359f20989a47eb5 ] The PCI host controller on PolarFire SoC has multiple Root Port instances, each with their own bridge and ctrl address spaces. The original binding has an "apb" register region, and it is expected to be set to the base address of the Root Complex register space. Some defines in the Linux driver were used to compute the addresses of the bridge and ctrl address ranges corresponding to Root Port instance 1. Some customers want to use Root Port instance 2 however, which requires changing the defines in the driver, which is clearly not a portable solution. The binding has been changed from a single register region to a pair, corresponding to the bridge and ctrl regions respectively, so modify the driver to read these regions directly from the devicetree rather than compute them from the base address of the abp region. To maintain backwards compatibility with the existing binding, the driver retains code to handle the "abp" reg and computes the base address of the bridge and ctrl regions using the defines if it is present. reg-names has always been a required property, so this is safe to do. Link: https://lore.kernel.org/r/20241107-surrender-brisket-287d563a5de1@spud Signed-off-by: Conor Dooley [bhelgaas: Capitalize PCIe spec terms] Signed-off-by: Bjorn Helgaas Stable-dep-of: 1390a33b3d04 ("PCI: microchip: Set inbound address translation for coherent or non-coherent mode") Signed-off-by: Sasha Levin

PCI: starfive: Enable controller runtime PM before probing host bridge

2024-12-14T19:04:04+00:00

[ Upstream commit 6168efbebace0db443185d4c6701ca8170a8788d ] A PCI controller device, e.g., StarFive, is parent to PCI host bridge device. We must enable runtime PM of the controller before enabling runtime PM of the host bridge, which will happen in pci_host_probe(), to avoid this warning: pcie-starfive 940000000.pcie: Enabling runtime PM for inactive device with active children Fix this issue by enabling StarFive controller device's runtime PM before calling pci_host_probe() in plda_pcie_host_init(). Link: https://lore.kernel.org/r/20241111-runtime_pm-v7-1-9c164eefcd87@quicinc.com Tested-by: Marek Szyprowski Signed-off-by: Mayank Rana [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam Signed-off-by: Sasha Levin

PCI: plda: Silence 'set affinity failed' warning

2024-07-29T17:46:35+00:00

Use MSI_FLAG_NO_AFFINITY, which keeps .irq_set_affinity() unset and allows migrate_one_irq() to exit right away, without warnings like this: IRQ...: set affinity failed(-22) Remove the .irq_set_affinity() implementation that is no longer needed. Link: https://lore.kernel.org/r/20240723132958.41320-10-marek.vasut+renesas@mailbox.org Signed-off-by: Marek Vasut [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas Reviewed-by: Manivannan Sadhasivam Acked-by: Thomas Gleixner

PCI: starfive: Add JH7110 PCIe controller

2024-05-28T16:15:30+00:00

Add StarFive JH7110 SoC PCIe controller platform driver code, JH7110 with PLDA host PCIe core. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-22-minda.chen@starfivetech.com Co-developed-by: Kevin Xie Signed-off-by: Minda Chen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Mason Huo

PCI: plda: Pass pci_host_bridge to plda_pcie_setup_iomems()

2024-05-28T16:15:29+00:00

plda_pcie_setup_iomems() needs the bridge->windows list from struct pci_host_bridge and is currently used only by pcie-microchip-host.c. This driver uses pci_host_common_probe(), which sets a pci_host_bridge as the drvdata, so plda_pcie_setup_iomems() used platform_get_drvdata() to find the pci_host_bridge. But we also want to use plda_pcie_setup_iomems() in the new pcie-starfive.c driver, which does not use pci_host_common_probe() and will have struct starfive_jh7110_pcie as its drvdata, so pass the pci_host_bridge directly to plda_pcie_setup_iomems() so it doesn't need platform_get_drvdata() to find it. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-9-minda.chen@starfivetech.com Signed-off-by: Minda Chen Signed-off-by: Krzysztof Wilczyński [bhelgaas: commit log, reorder to where this is needed] Signed-off-by: Bjorn Helgaas Reviewed-by: Conor Dooley

PCI: plda: Add host init/deinit and map bus functions

2024-05-28T16:15:29+00:00

Add PLDA host plda_pcie_host_init()/plda_pcie_host_deinit() and map bus function so vendors can use it to init PLDA PCIe host core. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-19-minda.chen@starfivetech.com Signed-off-by: Minda Chen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Reviewed-by: Mason Huo

PCI: plda: Add event bitmap field to struct plda_pcie_rp

2024-05-28T16:15:29+00:00

PLDA DMA interrupts are not all implemented, and the non-implemented interrupts should be masked. Add a bitmap field to mask the non-implemented interrupts. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-18-minda.chen@starfivetech.com Signed-off-by: Minda Chen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas

PCI: microchip: Move IRQ functions to pcie-plda-host.c

2024-05-28T16:15:29+00:00

Move IRQ related functions to common file pcie-plda-host.c The re-use code including MSI, INTx, event interrupts and IRQ init functions. Link: https://lore.kernel.org/linux-pci/20240328091835.14797-17-minda.chen@starfivetech.com Signed-off-by: Minda Chen Signed-off-by: Krzysztof Wilczyński Signed-off-by: Bjorn Helgaas Acked-by: Conor Dooley