kernel/linux.git/drivers/pci/controller/cadence, branch v7.2-rc5

Replace by more specific (c files)

2026-07-03T05:38:17+00:00

Replace the #include of by the more specific where applicable. For most cases the include can be dropped completely, only a few drivers need one or two headers added. Acked-by: Danilo Krummrich Acked-by: Takashi Sakamoto Acked-by: Bjorn Helgaas Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com Signed-off-by: Uwe Kleine-König (The Capable Hub)

Merge branch 'pci/controller/tlp_macros'

2026-06-23T22:32:23+00:00

- Add common TLP Type macros (MRd/Wr, IORd/Wr, CfgRd/Wr 0, CfgRd/Wr 1, Msg) and use them in aspeed, cadence, dwc, mediatek, tegra drivers (Hans Zhang) * pci/controller/tlp_macros: PCI: cadence: Use common TLP type macros PCI: dwc: Replace ATU type macros with common TLP type macros PCI: Add common TLP type macros and convert aspeed/mediatek

Merge branch 'pci/controller/rescan_lock'

2026-06-23T22:32:23+00:00

- Protect root bus removal with rescan lock in altera, brcmstb, cadence, dwc, iproc, mediatek, plda, rockchip to prevent use-after-free or crashes when racing with sysfs rescan or hotplug (Hans Zhang) * pci/controller/rescan_lock: PCI: rockchip: Protect root bus removal with rescan lock PCI: plda: Protect root bus removal with rescan lock PCI: mediatek: Protect root bus removal with rescan lock PCI: iproc: Protect root bus removal with rescan lock PCI: dwc: Protect root bus removal with rescan lock PCI: cadence: Protect root bus removal with rescan lock PCI: brcmstb: Protect root bus removal with rescan lock PCI: altera: Protect root bus removal with rescan lock

PCI: cadence-hpa: Add post-link delay

2026-06-23T19:33:48+00:00

The Cadence HPA (High Performance Architecture IP) specific link setup function cdns_pcie_hpa_host_link_setup() waits for the link to come up but does not implement the required 100 ms delay after link training completes for speeds > 5.0 GT/s (PCIe r6.0 sec 6.6.1). Add a call to pci_host_common_link_train_delay() immediately after the link is confirmed to be up, using the max_link_speed field. Also, in the HPA host setup function, read the device tree property "max-link-speed" to initialize max_link_speed if not already set by a glue driver. This ensures compliance for HPA-based platforms. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam [bhelgaas: driver tag "cadence: HPA:" -> "cadence-hpa:"] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20260518004246.1384532-4-18255117159@163.com

PCI: cadence: Protect root bus removal with rescan lock

2026-06-18T16:50:55+00:00

Hold the pci_rescan_remove_lock lock while stopping and removing a root bus to avoid racing with concurrent rescan or hotplug operations triggered via sysfs. Such races may lead to use-after-free issues or system crashes. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam [bhelgaas: commit log] Signed-off-by: Bjorn Helgaas Link: https://patch.msgid.link/20260521161822.132996-2-18255117159@163.com

PCI: cadence: Add post-link delay for LGA and j721e glue driver

2026-06-09T15:22:25+00:00

The Cadence LGA (Legacy Architecture IP) PCIe host controller currently lacks the mandatory 100 ms delay after link training completes for speeds > 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1. Add a 'max_link_speed' field to struct cdns_pcie. In the common host layer function cdns_pcie_host_start_link(), after the link has been successfully established, call pci_host_common_link_train_delay() to insert the required delay. For the j721e glue driver, set cdns_pcie.max_link_speed from the existing link speed logic. For other LGA-based glue drivers (sky1, sg2042), the common LGA host setup (pcie-cadence-host.c) provides a fallback reading of the device tree property "max-link-speed" when available. This ensures that the delay is not missed on those platforms once they enable the property. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260518004246.1384532-3-18255117159@163.com

PCI: cadence: Use common TLP type macros

2026-06-09T13:55:07+00:00

The Cadence HPA driver uses hardcoded constants (0x0, 0x2, 0x4, 0x5, 0x10) to program the outbound region type. Replace them with the newly introduced common TLP type macros from pci.h for better readability and maintainability. Signed-off-by: Hans Zhang <18255117159@163.com> Signed-off-by: Manivannan Sadhasivam Link: https://patch.msgid.link/20260516153657.65214-4-18255117159@163.com

Merge branch 'pci/controller/cadence-sky1'

2026-04-13T17:50:09+00:00

- Release ECAM config on probe failure (Felix Gu) * pci/controller/cadence-sky1: PCI: sky1: Use boolean true for is_rc field PCI: sky1: Fix missing cleanup of ECAM config on probe failure

Merge branch 'pci/controller/cadence-sg2042'

2026-04-13T17:50:08+00:00

- Add cadence core flags to disable advertising broken ASPM support (Yao Zi) - Disable ASPM L0s and L1 on Sophgo 2042 PCIe Root Ports that advertise support for them (Yao Zi) * pci/controller/cadence-sg2042: PCI: sg2042: Avoid L0s and L1 on Sophgo 2042 PCIe Root Ports PCI: cadence: Add flags for disabling ASPM capability for broken Root Ports

Merge branch 'pci/controller/cadence'

2026-04-13T17:50:08+00:00

- Implement byte/word config reads with dword (32-bit) reads because some Cadence controllers don't support sub-dword accesses (Aksh Garg) * pci/controller/cadence: PCI: cadence: Use cdns_pcie_read_sz() for byte or word read access