kernel/linux.git/drivers/pci/Makefile, branch v6.1.168

PCI/DOE: Add DOE mailbox support functions

2022-07-19T22:38:04+00:00

Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based mailbox with standard protocol discovery. Each mailbox is accessed through a DOE Extended Capability. Each DOE mailbox must support the DOE discovery protocol in addition to any number of additional protocols. Define core PCIe functionality to manage a single PCIe DOE mailbox at a defined config space offset. Functionality includes iterating, creating, query of supported protocol, and task submission. Destruction of the mailboxes is device managed. Cc: "Li, Ming" Cc: Bjorn Helgaas Cc: Matthew Wilcox Acked-by: Bjorn Helgaas Signed-off-by: Jonathan Cameron Co-developed-by: Ira Weiny Signed-off-by: Ira Weiny Link: https://lore.kernel.org/r/20220719205249.566684-4-ira.weiny@intel.com Signed-off-by: Dan Williams

PCI/VGA: Move vgaarb to drivers/pci

2022-03-10T00:30:46+00:00

The VGA arbiter is really PCI-specific and doesn't depend on any GPU things. Move it to the PCI subsystem. Note that misc_init() must be called before vga_arb_device_init(). These are both subsys_initcalls, so this ordering depends on the link order, which is determined by drivers/Makefile: obj-y += pci/ obj-y += char/ <-- misc_init() obj-y += gpu/ <-- vga_arb_device_init() (before this commit) The drivers/pci/ subsys_initcalls are called *before* misc_init(), so convert vga_arb_device_init() to subsys_initcall_sync(), which is called after *all* subsys_initcalls. Link: https://lore.kernel.org/r/20220224224753.297579-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas

PCI/MSI: Move code into a separate directory

2021-12-09T10:52:22+00:00

msi.c is getting larger and really could do with a splitup. Move it into its own directory to prepare for that. Signed-off-by: Thomas Gleixner Tested-by: Juergen Gross Reviewed-by: Jason Gunthorpe Acked-by: Bjorn Helgaas Link: https://lore.kernel.org/r/20211206210224.655043033@linutronix.de

PCI: Apply CONFIG_PCI_DEBUG to entire drivers/pci hierarchy

2021-02-09T21:10:20+00:00

CONFIG_PCI_DEBUG=y adds -DDEBUG to CFLAGS, which enables things like pr_debug() and dev_dbg() (and hence pci_dbg()). Previously we added -DDEBUG for files in drivers/pci/, but not files in subdirectories of drivers/pci/. Add -DDEBUG to CFLAGS for all files below drivers/pci/ so CONFIG_PCI_DEBUG applies to the entire hierarchy. [bhelgaas: commit log] Link: https://lore.kernel.org/r/1612438215-33105-1-git-send-email-yangyicong@hisilicon.com Signed-off-by: Junhao He Signed-off-by: Yicong Yang Signed-off-by: Bjorn Helgaas Reviewed-by: Krzysztof Wilczyński

PCI/MSI: Move MSI/MSI-X init to msi.c

2020-12-04T18:08:19+00:00

Move pci_msi_setup_pci_dev(), which disables MSI and MSI-X interrupts, from probe.c to msi.c so it's with all the other MSI code and more consistent with other capability initialization. This means we must compile msi.c always, even without CONFIG_PCI_MSI, so wrap the rest of msi.c in an #ifdef and adjust the Makefile accordingly. No functional change intended. Link: https://lore.kernel.org/r/20201203185110.1583077-2-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Thierry Reding

PCI: Allow building PCIe things without PCIEPORTBUS

2019-11-21T13:52:33+00:00

Some things in drivers/pci/pcie (aspm.c and ptm.c) do not depend on the PCIe portdrv, so we should be able to build them even if PCIEPORTBUS is not selected. Remove the PCIEPORTBUS guard from building pcie/. Link: https://lore.kernel.org/r/20191106222420.10216-6-helgaas@kernel.org Signed-off-by: Bjorn Helgaas Reviewed-by: Andrew Murray

PCI: OF: Allow of_pci_get_max_link_speed() to be used by PCI Endpoint drivers

2019-04-15T12:24:02+00:00

of_pci_get_max_link_speed() is built only if CONFIG_PCI is enabled. Make of_pci_get_max_link_speed() to be also used by PCI Endpoint controllers with just CONFIG_PCI_ENDPOINT enabled. Signed-off-by: Kishon Vijay Abraham I Signed-off-by: Sekhar Nori Signed-off-by: Lorenzo Pieralisi Acked-by: Bjorn Helgaas

PCI/ACPI: Allow ACPI to be built without CONFIG_PCI set

2018-12-20T09:19:49+00:00

We are compiling PCI code today for systems with ACPI and no PCI device present. Remove the useless code and reduce the tight dependency. Signed-off-by: Sinan Kaya Acked-by: Bjorn Helgaas # PCI parts Acked-by: Ingo Molnar Signed-off-by: Rafael J. Wysocki

Merge branch 'remotes/lorenzo/pci/controller-misc'

2018-10-20T16:45:47+00:00

- Remove redundant controller tests for "device_type == pci" (Rob Herring) - Document R-Car E3 (R8A77990) bindings (Tho Vu) - Add device tree support for R-Car r8a7744 (Biju Das) - Drop unused mvebu PCIe capability code (Thomas Petazzoni) - Add shared PCI bridge emulation code (Thomas Petazzoni) - Convert mvebu to use shared PCI bridge emulation (Thomas Petazzoni) - Add aardvark Root Port emulation (Thomas Petazzoni) * remotes/lorenzo/pci/controller-misc: PCI: aardvark: Implement emulated root PCI bridge config space PCI: mvebu: Convert to PCI emulated bridge config space PCI: mvebu: Drop unused PCI express capability code PCI: Introduce PCI bridge emulated config space common logic dt-bindings: PCI: rcar: Add device tree support for r8a7744 dt-bindings: PCI: rcar: Add device tree support for r8a7744 DT: pci: rcar-pci: document R8A77990 bindings PCI: Remove unnecessary check of device_type == pci

PCI: Introduce PCI bridge emulated config space common logic

2018-10-18T16:50:19+00:00

Some PCI host controllers do not expose a configuration space for the root port PCI bridge. Due to this, the Marvell Armada 370/38x/XP PCI controller driver (pci-mvebu) emulates a root port PCI bridge configuration space, and uses that to (among other things) dynamically create the memory windows that correspond to the PCI MEM and I/O regions. Since we now need to add a very similar logic for the Marvell Armada 37xx PCI controller driver (pci-aardvark), instead of duplicating the code, we create in this commit a common logic called pci-bridge-emul. The idea of this logic is to emulate a root port PCI bridge configuration space by providing configuration space read/write operations, and faking behind the scenes the configuration space of a PCI bridge. A PCI host controller driver simply has to call pci_bridge_emul_conf_read() and pci_bridge_emul_conf_write() to read/write the configuration space of the bridge. By default, the PCI bridge configuration space is simply emulated by a chunk of memory, but the PCI host controller can override the behavior of the read and write operations on a per-register basis to do additional actions if needed. We take care of complying with the behavior of the PCI configuration space registers in terms of bits that are read-write, read-only, reserved and write-1-to-clear. Signed-off-by: Thomas Petazzoni Signed-off-by: Lorenzo Pieralisi Acked-by: Bjorn Helgaas Reviewed-by: Russell King