kernel/linux.git/drivers/nvmem/sunxi_sid.c, branch v6.3

nvmem: sunxi_sid: Drop the workaround on A64

2023-02-06T18:06:58+00:00

Now that the SRAM readout code is fixed by using 32-bit accesses, it always returns the same values as register readout, so the A64 variant no longer needs the workaround. This makes the D1 variant structure redundant, so remove it. Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230206134356.839737-2-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Always use 32-bit MMIO reads

2023-01-28T13:36:28+00:00

The SID SRAM on at least some SoCs (A64 and D1) returns different values when read with bus cycles narrower than 32 bits. This is not immediately obvious, because memcpy_fromio() uses word-size accesses as long as enough data is being copied. The vendor driver always uses 32-bit MMIO reads, so do the same here. This is faster than the register-based method, which is currently used as a workaround on A64. And it fixes the values returned on D1, where the SRAM method was being used. The special case for the last word is needed to maintain .word_size == 1 for sysfs ABI compatibility, as noted previously in commit de2a3eaea552 ("nvmem: sunxi_sid: Optimize register read-out method"). Fixes: 07ae4fde9efa ("nvmem: sunxi_sid: Add support for D1 variant") Cc: stable@vger.kernel.org Tested-by: Heiko Stuebner Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20230127104015.23839-3-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Add support for D1 variant

2022-02-21T17:00:30+00:00

D1 has a smaller eFuse block than some other recent SoCs, and it no longer requires a workaround to read the eFuse data. Signed-off-by: Samuel Holland Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20220220151527.17216-7-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Set type to OTP

2021-06-11T08:57:52+00:00

This device currently reports an "Unknown" type in sysfs. Since it is an eFuse hardware device, set its type to OTP. Signed-off-by: Samuel Holland Acked-by: Chen-Yu Tsai Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20210611083348.20170-7-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: fix A64 SID controller support

2019-08-18T10:56:52+00:00

Like in H3, A64 SID controller doesn't return correct data when using direct access. It appears that on A64, SID needs 8 bytes of word_size. Workaround is to enable read by registers. Signed-off-by: Stefan Mavrodiev Acked-by: Chen-Yu Tsai Tested-by: Vasily Khoruzhick Signed-off-by: Srinivas Kandagatla Link: https://lore.kernel.org/r/20190818093345.29647-4-srinivas.kandagatla@linaro.org Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Support SID on H6

2019-04-25T17:43:13+00:00

Add support for H6's SID controller. It supports 4K-bit EFUSE, bigger than before. Signed-off-by: Yangtao Li Acked-by: Maxime Ripard Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi-sid: convert to SPDX license tags

2019-04-25T17:43:13+00:00

Updates license to use SPDX-License-Identifier. Acked-by: Maxime Ripard Signed-off-by: Yangtao Li Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Support SID on A83T and H5

2019-04-25T17:43:12+00:00

The device tree binding already lists compatible strings for these two SoCs. They don't have the defect as seen on the H3, and the size and register layout is the same as the A64. Furthermore, the driver does not include nvmem cell definitions. Add support for these two compatible strings, re-using the config for the A64. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Read out data in native format

2019-04-25T17:43:11+00:00

Originally the SID e-fuses were thought to be in big-endian format. Later sources show that they are in fact native or little-endian. The most compelling evidence is the thermal sensor calibration data, which is a set of one to three 16-bit values. In native-endian they are in 16-bit cells with increasing offsets, whereas with big-endian they are in the wrong order, and a gap with no data will show if there are one or three cells. Switch to a native endian representation for the nvmem device. For the H3, the register read-out method was already returning data in native endian. This only affects the other SoCs. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman

nvmem: sunxi_sid: Dynamically allocate nvmem_config structure

2019-04-25T17:43:11+00:00

The sunxi_sid driver currently uses a statically allocated nvmem_config structure that is updated at probe time. This is sub-optimal as it limits the driver to one instance, and also takes up space even if the device is not present. Modify the driver to allocate the nvmem_config structure at probe time, plugging in the desired parameters along the way. Signed-off-by: Chen-Yu Tsai Acked-by: Maxime Ripard Signed-off-by: Srinivas Kandagatla Signed-off-by: Greg Kroah-Hartman