kernel/linux.git/drivers/net/phy/realtek, branch v7.2-rc2

net: phy: realtek: Clear MDIO_AN_10GBT_CTRL_ADV10G bit

2026-06-25T01:41:00+00:00

On RTL8127A connected to a link partner that advertises 10000baseT speed cannot be changed to anything other than 10000baseT as 10GbE is always advertised regardless of any setting. Fix this by clearing MDIO_AN_10GBT_CTRL_ADV10G bit in rtl822x_config_aneg()'s call to phy_modify_mmd_changed(). Fixes: 83d962316128 ("net: phy: realtek: add RTL8127-internal PHY") Reviewed-by: Maxime Chevallier Signed-off-by: Jan Klos Link: https://patch.msgid.link/20260620011956.37181-1-honza.klos@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: support MDI swapping for RTL8226-CG

2026-05-20T23:50:24+00:00

Add support for configuring swapping of MDI pairs (ABCD->DCBA) when the property "enet-phy-pair-order" is specified. Unfortunately, no documentation about this feature is available, but this implementation still tries to avoid magic numbers and raw register numbers where it seems clear what is going on. As it is unknown whether the patching step can be safely reversed, only enabling MDI swapping is fully supported. A value of "0" for the "enet- phy-pair-order" property is not accepted if the PHY has already been patched for MDI swapping (however, this should not occur in practice). Some other Realtek PHYs also support similar mechanisms: - RTL8221B-VB-CG allows to configure MDI swapping via the same register, but does not need the additional patching step. However, it is unclear whether a driver implementation for that PHY is necessary, as it is known to support configuration via strapping pins (which is working fine at least in Zyxel XGS1210-12 rev B1). - The patching step seems to match the one for the integrated PHYs of some Realtek PCIe/USB NICs (see for example the r8152 driver). For now, only implement this for the RTL8226-CG PHY, where it is needed for the switches Zyxel XGS1010-12 rev A1 and XGS1210-12 rev A1. Signed-off-by: Jan Hoffmann Link: https://patch.msgid.link/20260516190456.387768-1-jan@3e8.eu Signed-off-by: Jakub Kicinski

net: phy: realtek: replace magic number with register bit macros

2026-05-05T02:22:21+00:00

Replace magic number with register bit macros. The description of the RTL8211B interrupt register is obtained from publicly available datasheet (RTL8211B(L) Rev. 1.5 Datasheet) Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: Daniel Golle Link: https://patch.msgid.link/20260502092857.156831-1-olek2@wp.pl Signed-off-by: Jakub Kicinski

net: phy: realtek: Add support for PHY LEDs on RTL8221B

2026-05-05T01:38:36+00:00

Realtek RTL8221B Ethernet PHY supports three LED pins which are used to indicate link status and activity. Add netdev trigger support for them. Signed-off-by: Chukun Pan Reviewed-by: Andrew Lunn Link: https://patch.msgid.link/20260501100002.755672-1-amadeus@jmu.edu.cn Signed-off-by: Jakub Kicinski

net: phy: realtek: use LEDCR page number define on RTL8211F

2026-04-13T23:38:25+00:00

Replace the magic number with an existing define for the LEDCR register page number on the RTL8211F. Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: Daniel Golle Link: https://patch.msgid.link/20260411105150.184577-1-olek2@wp.pl Signed-off-by: Jakub Kicinski

net: phy: realtek: convert RTL8211F to .disable_autonomous_eee

2026-04-12T18:33:23+00:00

The RTL8211F previously unconditionally disabled PHY-mode EEE in config_init. Convert this to use the new .disable_autonomous_eee callback so it is only disabled when the MAC indicates EEE support via phy_support_eee(). This preserves PHY-autonomous EEE for MACs that do not support EEE, while still disabling it when the MAC manages LPI. Signed-off-by: Nicolai Buchwitz Link: https://patch.msgid.link/20260406-devel-autonomous-eee-v1-3-b335e7143711@tipi-net.de Signed-off-by: Jakub Kicinski

net: phy: realtek: Add property to enable SSC

2026-04-10T03:01:52+00:00

Add support for spread spectrum clocking (SSC) on RTL8211F(D)(I)-CG, RTL8211FS(I)(-VS)-CG, RTL8211FG(I)(-VS)-CG PHYs. The implementation follows EMI improvement application note Rev. 1.2 for these PHYs. The current implementation enables SSC for both RXC and SYSCLK clock signals. Introduce DT properties 'realtek,clkout-ssc-enable', 'realtek,rxc-ssc-enable' and 'realtek,sysclk-ssc-enable' which control CLKOUT, RXC and SYSCLK SSC spread spectrum clocking enablement on these signals. Signed-off-by: Marek Vasut Link: https://patch.msgid.link/20260405233008.148974-3-marek.vasut@mailbox.org Signed-off-by: Jakub Kicinski

net: phy: realtek: get rid of magic numbers in rtl8201_config_intr()

2026-04-09T02:17:17+00:00

Replace the magic numbers with defines. Register names were obtained from publicly available documentation[1]. This should make it clear what's going on in the code. 1. RTL8201F/RTL8201FL/RTL8201FN Rev. 1.4 Datasheet Signed-off-by: Aleksander Jan Bajkowski Reviewed-by: Daniel Golle Reviewed-by: Nicolai Buchwitz nb@tipi-net.de Link: https://patch.msgid.link/20260406201222.1043396-1-olek2@wp.pl Signed-off-by: Jakub Kicinski

net: phy: realtek: add RTL8224 polarity support

2026-03-21T02:12:46+00:00

The RTL8224 has a register to configure the polarity of every pair of each port. It provides device designers more flexbility when wiring the chip. Unfortunately, the register is left in an unknown state after a reset. Thus on devices where the bootloader don't initialize it, the driver has to do it to detect and use a link. The MDI polarity swap can be set in the device tree using the property enet-phy-pair-polarity. The u32 value is a bitfield where bit[0..3] control the polarity of pairs A..D. Signed-off-by: Damien Dejean Link: https://patch.msgid.link/20260318215502.106528-5-dam.dejean@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: add RTL8224 pair order support

2026-03-21T02:12:46+00:00

The RTL8224 has a register to configure a pair swap (from ABCD order to DCBA) providing PCB designers more flexbility when wiring the chip. The swap parameter has to be set correctly for each of the 4 ports before the chip can detect a link. After a reset, this register is (unfortunately) left in a random state, thus it has to be initialized. On most of the devices the bootloader does it once for all and we can rely on the value set, on some other it is not and the kernel has to do it. The MDI pair swap can be set in the device tree using the property enet-phy-pair-order. The property is set to 0 to keep the default order (ABCD), or 1 to reverse the pairs (DCBA). Signed-off-by: Damien Dejean Link: https://patch.msgid.link/20260318215502.106528-3-dam.dejean@gmail.com Signed-off-by: Jakub Kicinski