kernel/linux.git/drivers/net/phy/realtek.c, branch linux-6.9.y

Merge git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net

2024-02-22T23:29:26+00:00

Cross-merge networking fixes after downstream PR. Conflicts: net/ipv4/udp.c f796feabb9f5 ("udp: add local "peek offset enabled" flag") 56667da7399e ("net: implement lockless setsockopt(SO_PEEK_OFF)") Adjacent changes: net/unix/garbage.c aa82ac51d633 ("af_unix: Drop oob_skb ref before purging queue in GC.") 11498715f266 ("af_unix: Remove io_uring code for GC.") Signed-off-by: Jakub Kicinski

net: phy: realtek: Fix rtl8211f_config_init() for RTL8211F(D)(I)-VD-CG PHY

2024-02-22T08:53:54+00:00

Commit bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG") extended support of the driver from the existing support for RTL8211F(D)(I)-CG PHY to the newer RTL8211F(D)(I)-VD-CG PHY. While that commit indicated that the RTL8211F_PHYCR2 register is not supported by the "VD-CG" PHY model and therefore updated the corresponding section in rtl8211f_config_init() to be invoked conditionally, the call to "genphy_soft_reset()" was left as-is, when it should have also been invoked conditionally. This is because the call to "genphy_soft_reset()" was first introduced by the commit 0a4355c2b7f8 ("net: phy: realtek: add dt property to disable CLKOUT clock") since the RTL8211F guide indicates that a PHY reset should be issued after setting bits in the PHYCR2 register. As the PHYCR2 register is not applicable to the "VD-CG" PHY model, fix the rtl8211f_config_init() function by invoking "genphy_soft_reset()" conditionally based on the presence of the "PHYCR2" register. Fixes: bb726b753f75 ("net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG") Signed-off-by: Siddharth Vadapalli Reviewed-by: Simon Horman Link: https://lore.kernel.org/r/20240220070007.968762-1-s-vadapalli@ti.com Signed-off-by: Paolo Abeni

net: phy: realtek: use generic MDIO helpers to simplify the code

2024-02-09T22:00:24+00:00

Use generic MDIO helpers to simplify the code. Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/422ae70f-7305-45fd-ab3e-0dd604b9fd6c@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: add 5Gbps support to rtl822x_config_aneg()

2024-02-08T02:19:51+00:00

RTL8126 as an evolution of RTL8125 supports 5Gbps. rtl822x_config_aneg() is used by the PHY driver for the integrated PHY, therefore add 5Gbps support to it. Signed-off-by: Heiner Kallweit Link: https://lore.kernel.org/r/5644ab50-e3e9-477c-96db-05cd5bdc2563@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: use generic MDIO constants

2024-02-08T02:19:50+00:00

Drop the ad-hoc MDIO constants used in the driver and use generic constants instead. Signed-off-by: Marek Behún Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Link: https://lore.kernel.org/r/732a70d6-4191-4aae-8862-3716b062aa9e@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: add support for RTL8126A-integrated 5Gbps PHY

2024-02-03T04:45:00+00:00

A user reported that first consumer mainboards show up with a RTL8126A 5Gbps MAC/PHY. This adds support for the integrated PHY, which is also available stand-alone. From a PHY driver perspective it's treated the same as the 2.5Gbps PHY's, we just have to support the new PHY ID. Reported-by: Joe Salmeri Signed-off-by: Heiner Kallweit Reviewed-by: Andrew Lunn Tested-by: Joe Salmeri Link: https://lore.kernel.org/r/0c8e67ea-6505-43d1-bd51-94e7ecd6e222@gmail.com Signed-off-by: Jakub Kicinski

net: phy: realtek: Disable clock on suspend

2023-06-07T08:52:24+00:00

For PHYs that call rtl821x_probe() where an external clock can be configured, make sure that the clock is disabled when ->suspend() is called and enabled on resume. The PHY_ALWAYS_CALL_SUSPEND is added to ensure that the suspend function is actually always called. Reviewed-by: Florian Fainelli Signed-off-by: Detlev Casanova Signed-off-by: David S. Miller

net: phy: realtek: Add optional external PHY clock

2023-06-07T08:52:24+00:00

In some cases, the PHY can use an external clock source instead of a crystal. Add an optional clock in the phy node to make sure that the clock source is enabled, if specified, before probing. Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: Detlev Casanova Signed-off-by: David S. Miller

net: phy: realtek: add support for RTL8211F(D)(I)-VD-CG

2022-08-22T11:47:18+00:00

RTL8211F(D)(I)-VD-CG is the pin-to-pin upgrade chip from RTL8211F(D)(I)-CG. Add new PHY ID for this chip. It does not support RTL8211F_PHYCR2 anymore, so remove the w/r operation of this register. Signed-off-by: Clark Wang Signed-off-by: Wei Fang Signed-off-by: David S. Miller

net: phy: realtek: add support for RTL8365MB-VC internal PHYs

2021-10-18T13:02:56+00:00

The RTL8365MB-VC ethernet switch controller has 4 internal PHYs for its user-facing ports. All that is needed is to let the PHY driver core pick up the IRQ made available by the switch driver. Signed-off-by: Alvin Šipraga Reviewed-by: Florian Fainelli Reviewed-by: Linus Walleij Signed-off-by: David S. Miller