kernel/linux.git/drivers/net/phy/broadcom.c, branch v4.19.16

net: phy: broadcom: Enable 125 MHz clock on LED4 pin for BCM54612E by default.

2018-06-05T13:43:09+00:00

BCM54612E have 4 multi-functional LED pins that can be configured through register setting; the LED4 pin can be configured to a 125MHz reference clock output by setting the spare register. Since the dedicated CLK125 reference clock pin is not brought out on the 48-Pin MLP, the LED4 pin is the only pin to provide such function in this package, and therefore it is beneficial to just enable the reference clock by default. Signed-off-by: Kun Yi Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: add support for BCM89610 PHY

2018-05-04T16:45:55+00:00

It adds support for BCM89610 (Single-Port 10/100/1000BASE-T) transceiver which is used in P3310 Tegra186 platform. Signed-off-by: Bhadram Varka Signed-off-by: David S. Miller

net: phy: broadcom: Add entry for 5395 switch PHYs

2017-12-15T20:41:13+00:00

Add an entry for the builtin PHYs present in the Broadcom BCM5395 switch. This allows us to retrieve the PHY statistics among other things. Signed-off-by: Florian Fainelli Tested-by: Chris Healy Signed-off-by: David S. Miller

net: phy: broadcom: re-add mistakenly removed config settings

2017-12-04T16:17:08+00:00

Previous patch mistakenly removed three chip-specific config settings. Add them again. Fixes: 80274abafc60 "net: phy: remove generic settings for callbacks config_aneg and read_status from drivers" Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller

net: phy: remove generic settings for callbacks config_aneg and read_status from drivers

2017-12-01T20:42:21+00:00

Remove generic settings for callbacks config_aneg and read_status from drivers. Signed-off-by: Heiner Kallweit Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: support new device flag for setting master mode

2017-10-13T05:59:38+00:00

Some of Broadcom's PHYs run by default in slave mode with Automatic Slave/Master configuration disabled. It stops them from working properly with some devices. So far it has been verified for BCM54210E and BCM50212E which don't work well with Intel's I217-LM and I218-LM: http://ark.intel.com/products/60019/Intel-Ethernet-Connection-I217-LM http://ark.intel.com/products/71307/Intel-Ethernet-Connection-I218-LM I was told there is massive ping loss. This commit adds support for a new flag which can be set by an ethernet driver to fixup PHY setup. Signed-off-by: Rafał Miłecki Signed-off-by: David S. Miller

net: phy: Remove residual magic from PHY drivers

2017-05-16T19:58:18+00:00

commit fa8cddaf903c ("net phylib: Remove unnecessary condition check in phy") removed the only place where the PHY flag PHY_HAS_MAGICANEG was checked. But it left the flag being set in the drivers. Remove the flag. Signed-off-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: Allow BCM5481x PHYs to setup internal TX/RX clock delay

2017-05-01T02:56:19+00:00

This patch allows users to enable/disable internal TX and/or RX clock delay for BCM5481x series PHYs so as to satisfy RGMII timing specifications. On a particular platform, whether TX and/or RX clock delay is required depends on how PHY connected to the MAC IP. This requirement can be specified through "phy-mode" property in the platform device tree. Signed-off-by: Abhishek Shah Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: rehook BCM54612E specific init

2017-02-01T19:20:20+00:00

This extra BCM54612E code in PHY driver isn't really aneg specific. Even without it aneg works OK but the problem is no packets pass through PHY. Moreover putting this code inside config_aneg callback didn't allow resuming PHY correctly. When driver called phy_stop and phy_start it was putting PHY machine into RESUMING state. After that machine was switching into AN and NOLINK without ever calling phy_start_aneg. This prevented this extra setup from being called and PHY didn't work. This change has been verified to fix network on BCM47186B0 SoC device with BCM54612E. Signed-off-by: Rafał Miłecki Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

net: phy: broadcom: add support for BCM54210E

2017-01-27T16:29:18+00:00

It's Broadcom PHY simply described as single-port RGMII 10/100/1000BASE-T PHY. It requires disabling delay skew and GTXCLK bits. Signed-off-by: Rafał Miłecki Signed-off-by: David S. Miller