kernel/linux.git/drivers/net/phy/adin.c, branch v5.10.264

treewide: Use fallthrough pseudo-keyword

2020-08-23T22:36:59+00:00

Replace the existing /* fall through */ comments and its variants with the new pseudo-keyword macro fallthrough[1]. Also, remove unnecessary fall-through markings when it is the case. [1] https://www.kernel.org/doc/html/v5.7/process/deprecated.html?highlight=fallthrough#implicit-switch-case-fall-through Signed-off-by: Gustavo A. R. Silva

net: phy: Fixup parameters in kerneldoc

2020-07-07T19:47:10+00:00

Correct the kerneldoc for a few structure and function calls, as reported by C=1 W=1. Cc: Alexandru Ardelean Reviewed-by: Florian Fainelli Signed-off-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: adin: fix a warning about msleep

2020-01-19T15:06:42+00:00

found a warning by the following command: ./scripts/checkpatch.pl -f drivers/net/phy/adin.c WARNING: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst #628: FILE: drivers/net/phy/adin.c:628: + msleep(10); Signed-off-by: Dejin Zheng Signed-off-by: David S. Miller

net: phy: adin: const-ify static data

2020-01-17T10:38:08+00:00

Some bits of static data should have been made const from the start. This change adds the const qualifier where appropriate. Reviewed-by: Andrew Lunn Signed-off-by: Alexandru Ardelean Signed-off-by: David S. Miller

net: phy: adin: implement Energy Detect Powerdown mode via phy-tunable

2019-09-16T20:02:45+00:00

This driver becomes the first user of the kernel's `ETHTOOL_PHY_EDPD` phy-tunable feature. EDPD is also enabled by default on PHY config_init, but can be disabled via the phy-tunable control. When enabling EDPD, it's also a good idea (for the ADIN PHYs) to enable TX periodic pulses, so that in case the other PHY is also on EDPD mode, there is no lock-up situation where both sides are waiting for the other to transmit. Via the phy-tunable control, TX pulses can be disabled if specifying 0 `tx-interval` via ethtool. The ADIN PHY supports only fixed 1 second intervals; they cannot be configured. That is why the acceptable values are 1, ETHTOOL_PHY_EDPD_DFLT_TX_MSECS and ETHTOOL_PHY_EDPD_NO_TX (which disables TX pulses). Reviewed-by: Florian Fainelli Signed-off-by: Alexandru Ardelean Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: remove calls to genphy_config_init

2019-08-17T19:34:50+00:00

Supported PHY features are either auto-detected or explicitly set. In both cases calling genphy_config_init isn't needed. All that genphy_config_init does is removing features that are set as supported but can't be auto-detected. Basically it duplicates the code in genphy_read_abilities. Therefore remove such calls from all PHY drivers. v2: - remove call also from new adin PHY driver v3: - pass NULL as config_init function pointer for dp83848 Signed-off-by: Heiner Kallweit Signed-off-by: David S. Miller

net: phy: adin: add ethtool get_stats support

2019-08-16T18:56:26+00:00

This change implements retrieving all the error counters from the PHY. The counters require that the RxErrCnt register (0x0014) be read first, after which copies of the counters are latched into the registers. This ensures that all registers read after RxErrCnt are synchronized at the moment that they are read. The counter values need to be accumulated by the driver, as each time that RxErrCnt is read, the values that are latched are the ones that have incremented from the last read. Signed-off-by: Alexandru Ardelean Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: adin: implement downshift configuration via phy-tunable

2019-08-16T18:56:26+00:00

Down-speed auto-negotiation may not always be enabled, in which case the PHY won't down-shift to 100 or 10 during auto-negotiation. This change enables downshift and configures the number of retries to default 4 (which is also in the datasheet The downshift control mechanism can also be controlled via the phy-tunable interface (ETHTOOL_PHY_DOWNSHIFT control). The change has been adapted from the Aquantia PHY driver. Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: Alexandru Ardelean Signed-off-by: David S. Miller

net: phy: adin: implement PHY subsystem software reset

2019-08-16T18:56:26+00:00

The ADIN PHYs supports 4 types of reset: 1. The standard PHY reset via BMCR_RESET bit in MII_BMCR reg 2. Reset via GPIO 3. Reset via reg GeSftRst (0xff0c) & reload previous pin configs 4. Reset via reg GeSftRst (0xff0c) & request new pin configs Resets 2, 3 & 4 are almost identical, with the exception that the crystal oscillator is available during reset for 2. This change implements subsystem software reset via the GeSftRst and reloading the previous pin configuration (so reset number 3). This will also reset the PHY core regs (similar to reset 1). Since writing bit 1 to reg GeSftRst is self-clearing, the only thing that can be done, is to write to that register, wait a specific amount of time (10 milliseconds should be enough) and try to read back and check if there are no errors on read. A busy-wait-read won't work well, and may sometimes work or not work. In case phylib is configured to also do a reset via GPIO, the ADIN PHY may be reset twice when the PHY device registers, but that isn't a problem, since it's being done on boot (or PHY device register). Signed-off-by: Alexandru Ardelean Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

net: phy: adin: add EEE translation layer from Clause 45 to Clause 22

2019-08-16T18:56:26+00:00

The ADIN1200 & ADIN1300 PHYs support EEE by using standard Clause 45 access to access MMD registers for EEE. The EEE register addresses (when using Clause 22) are available at different addresses (than Clause 45), and since accessing these regs (via Clause 22) needs a special mechanism, a translation table is required to convert these addresses. For Clause 45, this is not needed since the driver will likely never use this access mode. Reviewed-by: Florian Fainelli Reviewed-by: Andrew Lunn Signed-off-by: Alexandru Ardelean Signed-off-by: David S. Miller