kernel/linux.git/drivers/net/pcs, branch v6.18.21

net: pcs: pcs-mtk-lynxi: report in-band capability for 2500Base-X

2026-01-30T09:32:21+00:00

[ Upstream commit e8ca461f7d19464b47c64fe4cf2f83162421bcc0 ] It turns out that 2500Base-X actually works fine with in-band status on MediaTek's LynxI PCS -- I wrongly concluded it didn't because it is broken in all the copper SFP modules and GPON sticks I used for testing. Hence report LINK_INBAND_ENABLE also for 2500Base-X mode. This reverts most of commit a003c38d9bbb ("net: pcs: pcs-mtk-lynxi: correctly report in-band status capabilities"). The removal of the QSGMII interface mode was correct and is left untouched. Link: https://github.com/openwrt/openwrt/issues/21436 Fixes: a003c38d9bbb ("net: pcs: pcs-mtk-lynxi: correctly report in-band status capabilities") Signed-off-by: Daniel Golle Link: https://patch.msgid.link/b1cf26157b63fee838be09ae810497fb22fd8104.1768961746.git.daniel@makrotopia.org Signed-off-by: Jakub Kicinski Signed-off-by: Sasha Levin

net: pcs: Kconfig: Fix unmet dependency warning

2025-09-17T21:57:52+00:00

Fix the Kconfig dependencies for PCS_RZN1_MIIC to avoid the unmet direct dependency warning when enabling DWMAC_RENESAS_GBETH. The PCS driver is used on multiple Renesas SoCs including RZ/N1, RZ/N2H and RZ/T2H, but the existing condition only allowed ARCH_RZN1, ARCH_R9A09G077, or ARCH_R9A09G087. This conflicted with the GBETH/GMAC driver which selects PCS_RZN1_MIIC under ARCH_RENESAS. Update the dependency to ARCH_RENESAS || COMPILE_TEST so that the PCS driver is available on all Renesas platforms. Fixes: 08f89e42121d ("net: pcs: rzn1-miic: Add RZ/T2H MIIC support") Reported-by: Linux Kernel Functional Testing Closes: https://lore.kernel.org/all/aMlgg_QpJOEDGcEA@monster/ Signed-off-by: Lad Prabhakar Reviewed-by: Geert Uytterhoeven Link: https://patch.msgid.link/20250916162335.3339558-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Add RZ/T2H MIIC support

2025-09-16T00:44:36+00:00

Add support for the Renesas RZ/T2H MIIC by defining SoC-specific modctrl match tables, register map, and string representations for converters and ports. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-10-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Add per-SoC control for MIIC register unlock/lock

2025-09-16T00:44:36+00:00

Make MIIC accessory register unlock/lock behaviour selectable via SoC/OF data. Add init_unlock_lock_regs and miic_write to struct miic_of_data so the driver can either perform the traditional global unlock sequence (as used on RZ/N1) or use a different policy for other SoCs (for example RZ/T2H, which does not require leaving registers unlocked). miic_reg_writel() now calls the per-SoC miic_write callback to perform register writes. Provide miic_reg_writel_unlocked() as the default writer and set it for the RZ/N1 OF data so existing platforms keep the same behaviour. Add a miic_unlock_regs() helper that implements the accessory register unlock sequence so the unlock/lock sequence can be reused where needed (for example when a SoC requires explicit unlock/lock around individual accesses). This change is preparatory work for supporting RZ/T2H. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-9-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Add support to handle resets

2025-09-16T00:44:36+00:00

Add reset-line handling to the RZN1 MIIC driver and move reset configuration into the SoC/OF data. Introduce MIIC_MAX_NUM_RSTS (= 2), add storage for reset_control_bulk_data in struct miic and add reset_ids and reset_count fields to miic_of_data. When reset_ids are present in the OF data, the driver obtains the reset lines with devm_reset_control_bulk_get_exclusive(), deasserts them during probe and registers a devres action to assert them on remove or on error. This change is preparatory work to support the RZ/T2H SoC, which exposes two reset lines for the ETHSS IP. The driver remains backward compatible for platforms that do not provide reset lines. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-8-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Make switch mode mask SoC-specific

2025-09-16T00:44:36+00:00

Move the hardcoded switch mode mask definition into the SoC-specific miic_of_data structure. This allows each SoC to define its own mask value rather than relying on a single fixed constant. For RZ/N1 the mask remains GENMASK(4, 0). This is in preparation for adding support for RZ/T2H, where the switch mode mask is GENMASK(2, 0). Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-7-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: move port range handling into SoC data

2025-09-16T00:44:36+00:00

Define per-SoC miic_port_start and miic_port_max fields in struct miic_of_data and use them to validate the device-tree "reg" port number and to compute the driver's internal zero-based port index as (port - miic_port_start). Replace uses of the hard-coded MIIC_MAX_NR_PORTS with the SoC-provided miic_port_max when iterating over ports. On RZ/N1 the MIIC ports are numbered 1..5, whereas RZ/T2H numbers its MIIC ports 0..3. By making the port base and range part of the OF data the driver no longer assumes a fixed numbering scheme and can support SoCs that enumerate ports from either zero or one and that expose different numbers of ports. This change is preparatory work for adding RZ/T2H support. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-6-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Move configuration data to SoC-specific struct

2025-09-16T00:44:36+00:00

Move configuration data such as the modctrl matching table, converter count, and string lookup tables into the SoC-specific miic_of_data structure. Update the helper functions to use the per-SoC configuration instead of relying on fixed-size arrays or global tables, and allocate DT configuration memory dynamically. This refactoring keeps the existing RZ/N1 support intact while preparing the driver to handle the different configuration requirements of the RZ/T2H SoC. Signed-off-by: Lad Prabhakar Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-5-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Add missing include files

2025-09-16T00:44:35+00:00

The pcs-rzn1-miic driver makes use of ARRAY_SIZE(), BIT() and GENMASK() macros but does not explicitly include the headers where they are defined. Add the missing and includes. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-4-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski

net: pcs: rzn1-miic: Drop trailing comma from of_device_id table

2025-09-16T00:44:35+00:00

Remove the trailing comma after the sentinel entry in the of_device_id match table. Signed-off-by: Lad Prabhakar Reviewed-by: Andrew Lunn Tested-by: Wolfram Sang Link: https://patch.msgid.link/20250910204132.319975-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Jakub Kicinski