kernel/linux.git/drivers/net/dsa, branch v4.4.8

net: dsa: fix mv88e6xxx switches

2016-03-03T23:07:04+00:00

[ Upstream commit db0e51afa481088e6396f11e02018d64113a6578 ] Since commit 76e398a62712 ("net: dsa: use switchdev obj for VLAN add/del ops"), the Marvell 88E6xxx switch has been unable to pass traffic between ports - any received traffic is discarded by the switch. Taking a port out of bridge mode and configuring a vlan on it also the port to start passing traffic. With the debugfs files re-instated to allow debug of this issue by comparing the register settings between the working and non-working case, the reason becomes clear: GLOBAL GLOBAL2 SERDES 0 1 2 3 4 5 6 - 7: 1111 707f 2001 2 2 2 2 2 0 2 + 7: 1111 707f 2001 1 1 1 1 1 0 1 Register 7 for the ports is the default vlan tag register, and in the non-working setup, it has been set to 2, despite vlan 2 not being configured. This causes the switch to drop all packets coming in to these ports. The working setup has the default vlan tag register set to 1, which is the default vlan when none is configured. Inspection of the code reveals why. The code prior to this commit was: - for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { ... - if (!err && vlan->flags & BRIDGE_VLAN_INFO_PVID) - err = ds->drv->port_pvid_set(ds, p->port, vid); but the new code is: + for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { ... + } ... + if (pvid) + err = _mv88e6xxx_port_pvid_set(ds, port, vid); This causes the new code to always set the default vlan to one higher than the old code. Fix this. Fixes: 76e398a62712 ("net: dsa: use switchdev obj for VLAN add/del ops") Cc: Signed-off-by: Russell King Signed-off-by: David S. Miller Signed-off-by: Greg Kroah-Hartman

net: dsa: mv88e6060: replace magic values with register defines

2015-11-16T01:16:16+00:00

To align with the mv88e6xxx code, use the register defines to access all the register addresses and bit fields. Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Signed-off-by: David S. Miller

net: dsa: mv88e6060: add register defines header file

2015-11-16T01:16:16+00:00

To align with the mv88e6xxx code, add a similar header file with all the register defines. The file is based on the mv88e6xxx header for coherency. Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Acked-by: Vivien Didelot Signed-off-by: David S. Miller

net: dsa: mv88e6060: use the correct bit shift for mac0

2015-11-16T01:16:16+00:00

According to the mv88e6060 datasheet, the first mac byte must be at position 9 instead of 8 since the bit 8 is used to select if the mac address must differ for each port for Pause frames. Use the correct shift and set the same mac address for all port. Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Signed-off-by: David S. Miller

net: dsa: mv88e6060: use the correct MaxFrameSize bit

2015-11-16T01:16:16+00:00

According to the mv88e6060 datasheet, the MaxFrameSize bit position is 10 instead of 11 which is reserved. Use the bit correctly to setup max frame size to 1536. Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Signed-off-by: David S. Miller

net: dsa: mv88e6060: use the correct InitReady bit

2015-11-16T01:16:15+00:00

According to the mv88e6060 datasheet, the InitReady bit position is 11 and the polarity is inverted. Use the bit correctly to detect the end of initialization. Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Acked-by: Vivien Didelot Signed-off-by: David S. Miller

net: dsa: mv88e6060: remove poll_link callback

2015-11-16T01:16:15+00:00

As of mv88e6xxx remove the poll_link callback since the link state change polling is now handled by the phylib. Tested on a mv88e6060 B0 device with a TI DM816X SoC. Suggested-by: Andrew Lunn Acked-by: Andrew Lunn Signed-off-by: Neil Armstrong Signed-off-by: David S. Miller

net: dsa: mv88e6xxx: isolate unbridged ports

2015-11-05T18:37:23+00:00

The DSA documentation specifies that each port must be capable of forwarding frames to the CPU port. The last changes on bridging support for the mv88e6xxx driver broke this requirement for non-bridged ports. So as for the bridged ports, reserve a few VLANs (4000+) in the switch to isolate ports that have not been bridged yet. By default, a port will be isolated with the CPU and DSA ports. When the port joins a bridge, it will leave its reserved port. When it is removed from a bridge, it will join its reserved VLAN again. Fixes: 5fe7f68016ff ("net: dsa: mv88e6xxx: fix hardware bridging") Reported-by: Andrew Lunn Signed-off-by: Vivien Didelot Signed-off-by: David S. Miller

net: dsa: mv88e6xxx: include DSA ports in VLANs

2015-11-03T16:30:17+00:00

DSA ports must be members of a VLAN in order to ensure frame bridging between chained switch chips. Thus tag them in addition to the CPU port when adding a VLAN, and skip them when deleting a VLAN and reporting VLAN members. Also use the UNMODIFIED egress policy, so that frames egress on these ports as they ingress, tagged or untagged. Fixes: 0d3b33e60206 ("net: dsa: mv88e6xxx: add VLAN Load support") Reported-by: Andrew Lunn Signed-off-by: Vivien Didelot Signed-off-by: David S. Miller

net: dsa: mv88e6xxx: disable SA learning for DSA and CPU ports

2015-11-03T16:29:57+00:00

Frames with DSA headers passing to/from the CPU were taking place in the MAC learning on these ports, resulting in incorrect ATU entries. Disable learning on these ports. Signed-off-by: Andrew Lunn Signed-off-by: Vivien Didelot Signed-off-by: David S. Miller