kernel/linux.git/drivers/net/dsa, branch v4.3.1

dsa: mv88e6xxx: Enable forwarding for unknown to the CPU port

2015-09-30T04:06:51+00:00

Frames destined to an unknown address must be forwarded to the CPU port. Otherwise incoming ARP, dhcp leases, etc, do not work. Signed-off-by: Andrew Lunn Signed-off-by: David S. Miller

net: dsa: actually force the speed on the CPU port

2015-09-23T00:18:24+00:00

Commit 54d792f257c6 ("net: dsa: Centralise global and port setup code into mv88e6xxx.") merged in the 4.2 merge window broke the link speed forcing for the CPU port of Marvell DSA switches. The original code was: /* MAC Forcing register: don't force link, speed, duplex * or flow control state to any particular values on physical * ports, but force the CPU port and all DSA ports to 1000 Mb/s * full duplex. */ if (dsa_is_cpu_port(ds, p) || ds->dsa_port_mask & (1 << p)) REG_WRITE(addr, 0x01, 0x003e); else REG_WRITE(addr, 0x01, 0x0003); but the new code does a read-modify-write: reg = _mv88e6xxx_reg_read(ds, REG_PORT(port), PORT_PCS_CTRL); if (dsa_is_cpu_port(ds, port) || ds->dsa_port_mask & (1 << port)) { reg |= PORT_PCS_CTRL_FORCE_LINK | PORT_PCS_CTRL_LINK_UP | PORT_PCS_CTRL_DUPLEX_FULL | PORT_PCS_CTRL_FORCE_DUPLEX; if (mv88e6xxx_6065_family(ds)) reg |= PORT_PCS_CTRL_100; else reg |= PORT_PCS_CTRL_1000; The link speed in the PCS control register is a two bit field. Forcing the link speed in this way doesn't ensure that the bit field is set to the correct value - on the hardware I have here, the speed bitfield remains set to 0x03, resulting in the speed not being forced to gigabit. We must clear both bits before forcing the link speed. Fixes: 54d792f257c6 ("net: dsa: Centralise global and port setup code into mv88e6xxx.") Signed-off-by: Russell King Acked-by: Andrew Lunn Signed-off-by: David S. Miller

net: dsa: bcm_sf2: Fix 64-bits register writes

2015-09-09T21:14:22+00:00

The macro to write 64-bits quantities to the 32-bits register swapped the value and offsets arguments, we want to preserve the ordering of the arguments with respect to how writel() is implemented for instance: value first, offset/base second. Fixes: 246d7f773c13 ("net: dsa: add Broadcom SF2 switch driver") Signed-off-by: Florian Fainelli Reviewed-by: Vivien Didelot Signed-off-by: David S. Miller

net: dsa: bcm_sf2: Fix ageing conditions and operation

2015-09-09T05:27:35+00:00

The comparison check between cur_hw_state and hw_state is currently invalid because cur_hw_state is right shifted by G_MISTP_SHIFT, while hw_state is not, so we end-up comparing bits 2:0 with bits 7:5, which is going to cause an additional aging to occur. Fix this by not shifting cur_hw_state while reading it, but instead, mask the value with the appropriately shitfted bitmask. The other problem with the fast-ageing process is that we did not set the EN_AGE_DYNAMIC bit to request the ageing to occur for dynamically learned MAC addresses. Finally, write back 0 to the FAST_AGE_CTRL register to avoid leaving spurious bits sets from one operation to the other. Fixes: 12f460f23423 ("net: dsa: bcm_sf2: add HW bridging support") Signed-off-by: Florian Fainelli Signed-off-by: David S. Miller

net: dsa: mv88e6171: add hardware 802.1Q support

2015-09-07T02:50:50+00:00

The Marvell 88E6171 switch is in the 88E6351 family, which supports 802.1Q, thus add support from the generic mv88e6xxx functions. Signed-off-by: Vivien Didelot Reviewed-by: Andrew Lunn Signed-off-by: David S. Miller

dsa: mv88e6xxx: Don't poll forced interfaces for state changes

2015-08-31T21:48:02+00:00

When polling for link status, don't consider ports which have a forced link. Such ports don't monitor their phy or may not even have a phy. Signed-off-by: Andrew Lunn Acked-by: Florian Fainelli Signed-off-by: David S. Miller

dsa: mv88e6xxx: Set the RGMII delay based on phy interface

2015-08-31T21:48:02+00:00

Some Marvell switches allow the RGMII Rx and Tx clock to be delayed when the port is using RGMII. Have the adjust_link function look at the phy interface type and enable this delay as requested. Signed-off-by: Andrew Lunn Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

dsa: mv88e6xxx: Allow speed/duplex of port to be configured

2015-08-31T21:48:01+00:00

The current code sets user ports to perform auto negotiation using the phy. CPU and DSA ports are configured to full duplex and maximum speed the switch supports. There are however use cases where the CPU has a slower port, and when user ports have SFP modules with fixed speed. In these cases, port settings to be read from a fixed_phy devices. The switch driver then needs to implement the adjust_link op, so the port settings can be set. Signed-off-by: Andrew Lunn Reviewed-by: Florian Fainelli Signed-off-by: David S. Miller

net: dsa: mv88e6xxx: set 802.1Q mode to Fallback

2015-08-23T22:54:26+00:00

The current Secure port mode requires the port-based VLANs to also be valid in the 802.1Q VLAN Table Unit. The current hardware bridging support only configures the port-based VLANs, thus is broken. A new patchset is required to adapt the hardware bridging code to fully support the Secure port mode. In the meantime, change the 802.1Q mode of every ports to Fallback, which filtering is more permissive, and doesn't add this restriction to handle port-based and tagged-based VLANs. Fixes: 8efdda4a1b60 ("net: dsa: mv88e6xxx: use port 802.1Q mode Secure") Signed-off-by: Vivien Didelot Signed-off-by: David S. Miller

dsa: mv88e6xxx: Set DSA mode based on chip abilities

2015-08-18T21:17:21+00:00

Older devices only support a single DSA frame format, where as newer devices have two. Take this into account when configuring a DSA port. The port needs to be in plain old DSA mode, since this is a DSA link, where as the newer format can be used for the CPU port. Signed-off-by: Andrew Lunn Signed-off-by: David S. Miller