kernel/linux.git/drivers/misc/cxl/native.c, branch v6.12.80

cxl: Drop unused detach_spa()

2023-08-24T12:33:16+00:00

Clang warns: drivers/misc/cxl/native.c:272:20: error: unused function 'detach_spa' [-Werror,-Wunused-function] It was created as part of some refactoring in commit 05155772f642 ("cxl: Allocate and release the SPA with the AFU"), but has never been called in its current form. Drop it. Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman Link: https://msgid.link/20230823044803.737175-1-mpe@ellerman.id.au

cxl/ocxl: Prepare cleanup of powerpc's asm/prom.h

2022-05-11T13:06:39+00:00

powerpc's asm/prom.h brings some headers that it doesn't need itself. In order to clean it up, first add missing headers in users of asm/prom.h Signed-off-by: Christophe Leroy Acked-by: Frederic Barrat Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman Link: https://lore.kernel.org/r/a2bae89b280e7a7cb87889635d9911d6a245e780.1648833388.git.christophe.leroy@csgroup.eu

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152

2019-05-30T18:26:32+00:00

Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman

Revert "cxl: Add kernel API to allow a context to operate with relocate disabled"

2018-07-02T13:54:30+00:00

Remove abandonned capi support for the Mellanox CX4. The symbol 'cxl_set_translation_mode' is never called, so ctx->real_mode is always false. This reverts commit 7a0d85d313c2066712e530e668bc02bb741a685c. Signed-off-by: Alastair D'Silva Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman

cxl: Check if PSL data-cache is available before issue flush request

2018-03-13T04:50:26+00:00

PSL9D doesn't have a data-cache that needs to be flushed before resetting the card. However when cxl tries to flush data-cache on such a card, it times-out as PSL_Control register never indicates flush operation complete due to missing data-cache. This is usually indicated in the kernel logs with this message: "WARNING: cache flush timed out" To fix this the patch checks PSL_Debug register CDC-Field(BIT:27) which indicates the absence of a data-cache and sets a flag 'no_data_cache' in 'struct cxl_native' to indicate this. When cxl_data_cache_flush() is called it checks the flag and if set bails out early without requesting a data-cache flush operation to the PSL. Signed-off-by: Vaibhav Jain Acked-by: Andrew Donnellan Acked-by: Frederic Barrat Signed-off-by: Michael Ellerman

cxl: Add support for ASB_Notify on POWER9

2018-01-19T12:19:37+00:00

The POWER9 core supports a new feature: ASB_Notify which requires the support of the Special Purpose Register: TIDR. The ASB_Notify command, generated by the AFU, will attempt to wake-up the host thread identified by the particular LPID:PID:TID. This patch assign a unique TIDR (thread id) for the current thread which will be used in the process element entry. Signed-off-by: Christophe Lombard Reviewed-by: Philippe Bergheaud Acked-by: Frederic Barrat Reviewed-by: Vaibhav Jain Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman

cxl: Dump PSL_FIR register on PSL9 error irq

2017-10-13T08:41:57+00:00

For PSL9 currently we aren't dumping the PSL FIR register when a PSL error interrupt is triggered. Contents of this register are useful in debugging AFU issues. This patch fixes issue by adding a new service_layer_ops callback cxl_native_err_irq_dump_regs_psl9() to dump the PSL_FIR registers on a PSL error interrupt thereby bringing the behavior in line with PSL on POWER-8. Also the existing service_layer_ops callback for PSL8 has been renamed to cxl_native_err_irq_dump_regs_psl8(). Signed-off-by: Vaibhav Jain Acked-by: Frederic Barrat Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman

cxl: Rename register PSL9_FIR2 to PSL9_FIR_MASK

2017-10-10T09:17:49+00:00

PSL9 doesn't have a FIR2 register as was the case with PSL8. However currently the register definitions in 'cxl.h' have a definition for PSL9_FIR2 that actually points to PSL9_FIR_MASK register in the P1 area at offset 0x308. So this patch renames the def PSL9_FIR2 to PSL9_FIR_MASK and updates the references in the code to point to the new identifier. It also removes the code to dump contents of FIR2 (FIR_MASK actually) in cxl_native_irq_dump_regs_psl9(). Fixes: f24be42aab37 ("cxl: Add psl9 specific code") Reported-by: Frederic Barrat Signed-off-by: Vaibhav Jain Acked-by: Frederic Barrat Signed-off-by: Michael Ellerman

cxl: Set the valid bit in PE for dedicated mode

2017-10-03T05:03:46+00:00

Make sure to set the valid-bit in software-state field of the populated PE. This was earlier missing for dedicated mode AFUs, hence was causing a PSL freeze when the AFU was activated. Signed-off-by: Vaibhav Jain Acked-by: Frederic Barrat Acked-by: Andrew Donnellan Signed-off-by: Michael Ellerman

cxl: Export library to support IBM XSL

2017-07-03T13:07:03+00:00

This patch exports a in-kernel 'library' API which can be called by other drivers to help interacting with an IBM XSL on a POWER9 system. The XSL (Translation Service Layer) is a stripped down version of the PSL (Power Service Layer) used in some cards such as the Mellanox CX5. Like the PSL, it implements the CAIA architecture, but has a number of differences, mostly in it's implementation dependent registers. The XSL also uses a special DMA cxl mode, which uses a slightly different init sequence for the CAPP and PHB. Signed-off-by: Andrew Donnellan Signed-off-by: Christophe Lombard Acked-by: Frederic Barrat Signed-off-by: Michael Ellerman