kernel/linux.git/drivers/misc/amd-sbi, branch v7.1-rc5

misc: amd-sbi: Add device tree mapping for AMD SBRMI devices

2026-04-02T14:17:29+00:00

Add device tree mapping to enable SBRMI device support across different models and steppings on the AMD Venice platform. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20260318112711.2757467-3-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Add check to probe only SBRMI devices

2026-04-02T14:17:29+00:00

AMD OOB devices are differentiated by their Instance ID, with SBRMI assigned Instance ID 1. Since the device ID match does not consider the Instance ID, add an explicit check to restrict probing to only the SBRMI device and exclude other OOB devices. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20260318112711.2757467-2-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Add revision support for AMD Venice platform

2026-04-02T14:17:29+00:00

The AMD Venice platform uses revision 0x31 and a two-byte register address size. Add the revision to the CPUID and MCAMSR protocol functions to ensure correct protocol identification. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20260318112711.2757467-1-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Address CPUID extended function bits

2026-04-02T14:17:25+00:00

According to the UAPI header (amd-apml.h), the CPUID extended function capability is indicated by bits [55:48], but the driver currently checks bits [63:56]. Adjust the driver to use bits [55:48] so that extended function capability is detected correctly. Fixes: bb13a84ed6b7 ("misc: amd-sbi: Add support for CPUID protocol") Tested-by: Prathima L K Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20260318094706.2623258-1-Akshay.Gupta@amd.com Signed-off-by: Greg Kroah-Hartman

i3c: simplify combined i3c/i2c dependencies

2026-02-27T15:33:07+00:00

All combined i2c/i3c drivers appear to suffer from the same link time problem when CONFIG_I3C is set to 'm': arm-linux-gnueabi-ld: drivers/iio/magnetometer/mmc5633.o: in function `mmc5633_i3c_driver_init': mmc5633.c:(.init.text+0x30): undefined reference to `i3c_driver_register_with_owner' This was previously fixed every time by marking individual drivers as 'depends on I2C; depends on I3C || !I3C', but this gets tedious and is somewhat confusing. Add a Kconfig symbol 'I3C_OR_I2C' to help replace those dependencies, and use this in all the existing drivers that had already fixed it as well as the new mmc5633 driver. Reviewed-by: Jonathan Cameron Signed-off-by: Arnd Bergmann Acked-by: Guenter Roeck Acked-by: Jonathan Cameron Link: https://patch.msgid.link/20260204164216.544409-1-arnd@kernel.org Signed-off-by: Alexandre Belloni

Merge 6.18-rc3 into char-misc-next

2025-10-27T06:48:19+00:00

We need the fixes in here, and it resolves a merge conflict in: drivers/misc/amd-sbi/Kconfig Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Clarify that this is a BMC driver

2025-10-22T06:02:57+00:00

Add a sentence to the driver description to clarify that the sbrmi-i2c driver is intended to run on the BMC and not on the managed node. Add platform dependencies accordingly. Signed-off-by: Jean Delvare Link: https://lore.kernel.org/r/5c9f7100-0e59-4237-a252-43c3ee4802a2@amd.com Link: https://patch.msgid.link/20251016155040.0e86c102@endymion Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Extend support for MCAMSR protocol for rev 0x21

2025-10-22T05:59:57+00:00

- MCAMSR protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-6-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: Extend support for CPUID protocol for rev 0x21

2025-10-22T05:59:57+00:00

- CPUID protocol for revision 0x21 is updated to include the extended thread supported by the platform. - This modifies the existing protocol to include additional byte to provide high thread number. - New input structure is defined to address this, as the hardware protocol is tightly coupled with the input structure length Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-5-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman

misc: amd-sbi: CPUID/MCAMSR protocol for Revision 0x21

2025-10-22T05:59:57+00:00

- CPUID and MCAMSR protocol for newer platform with revision 0x21 and later is modified as per two byte register address size. - Modify the CPUID and MCAMSR protocol to return error, "-EOPNOTSUPP", for revision 0x21. - Next set of patches will add support for CPUID and MCAMSR for Turin and later platforms. Reviewed-by: Naveen Krishna Chatradhi Signed-off-by: Akshay Gupta Link: https://patch.msgid.link/20250915103649.1705078-4-akshay.gupta@amd.com Signed-off-by: Greg Kroah-Hartman