kernel/linux.git/drivers/memory, branch v5.15.7

memory: tegra20-emc: Add runtime dependency on devfreq governor module

2021-11-25T08:48:30+00:00

[ Upstream commit 14b43c20c283de36131da0cb44f3170b9ffa7630 ] Tegra20 EMC driver uses simple devfreq governor. Add simple devfreq governor to the list of the Tegra20 EMC driver module softdeps to allow userspace initramfs tools like dracut to automatically pull the devfreq module into ramfs image together with the EMC module. Reported-by: Nicolas Chauvet Suggested-by: Nicolas Chauvet Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20211019231524.888-1-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin

memory: fsl_ifc: fix leak of irq and nand_irq in fsl_ifc_ctrl_probe

2021-11-18T18:16:51+00:00

[ Upstream commit 4ed2f3545c2e5acfbccd7f85fea5b1a82e9862d7 ] The error handling code of fsl_ifc_ctrl_probe is problematic. When fsl_ifc_ctrl_init fails or request_irq of fsl_ifc_ctrl_dev->irq fails, it forgets to free the irq and nand_irq. Meanwhile, if request_irq of fsl_ifc_ctrl_dev->nand_irq fails, it will still free nand_irq even if the request_irq is not successful. Fix this by refactoring the error handling code. Fixes: d2ae2e20fbdd ("driver/memory:Move Freescale IFC driver to a common driver") Signed-off-by: Dongliang Mu Link: https://lore.kernel.org/r/20210925151434.8170-1-mudongliangabcd@gmail.com Signed-off-by: Krzysztof Kozlowski Signed-off-by: Sasha Levin

memory: renesas-rpc-if: Correct QSPI data transfer in Manual mode

2021-11-18T18:16:01+00:00

commit fff53a551db50f5edecaa0b29a64056ab8d2bbca upstream. This patch fixes 2 problems: [1] The output warning logs and data loss when performing mount/umount then remount the device with jffs2 format. [2] The access width of SMWDR[0:1]/SMRDR[0:1] register is wrong. This is the sample warning logs when performing mount/umount then remount the device with jffs2 format: jffs2: jffs2_scan_inode_node(): CRC failed on node at 0x031c51d4: Read 0x00034e00, calculated 0xadb272a7 The reason for issue [1] is that the writing data seems to get messed up. Data is only completed when the number of bytes is divisible by 4. If you only have 3 bytes of data left to write, 1 garbage byte is inserted after the end of the write stream. If you only have 2 bytes of data left to write, 2 bytes of '00' are added into the write stream. If you only have 1 byte of data left to write, 2 bytes of '00' are added into the write stream. 1 garbage byte is inserted after the end of the write stream. To solve problem [1], data must be written continuously in serial and the write stream ends when data is out. Following HW manual 62.2.15, access to SMWDR0 register should be in the same size as the transfer size specified in the SPIDE[3:0] bits in the manual mode enable setting register (SMENR). Be sure to access from address 0. So, in 16-bit transfer (SPIDE[3:0]=b'1100), SMWDR0 should be accessed by 16-bit width. Similar to SMWDR1, SMDDR0/1 registers. In current code, SMWDR0 register is accessed by regmap_write() that only set up to do 32-bit width. To solve problem [2], data must be written 16-bit or 8-bit when transferring 1-byte or 2-byte. Fixes: ca7d8b980b67 ("memory: add Renesas RPC-IF driver") Cc: Signed-off-by: Duc Nguyen [wsa: refactored to use regmap only via reg_read/reg_write] Signed-off-by: Wolfram Sang Tested-by: Lad Prabhakar Link: https://lore.kernel.org/r/20210922091007.5516-1-wsa+renesas@sang-engineering.com Signed-off-by: Krzysztof Kozlowski Signed-off-by: Greg Kroah-Hartman

Merge branch 'for-v5.15/omap-gpmc' into for-next

2021-07-29T07:03:32+00:00

memory: omap-gpmc: Drop custom PM calls with cpu_pm notifier

2021-07-29T07:02:27+00:00

We can now switch over to using cpu_pm instead of custom calls and make the context save and restore functions static. Let's also move the save and restore functions to avoid adding forward declarations for them. And get rid of the static data pointer while at it. Cc: Roger Quadros Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20210727101034.32148-2-tony@atomide.com Signed-off-by: Krzysztof Kozlowski

memory: omap-gpmc: Clear GPMC_CS_CONFIG7 register on restore if unused

2021-07-29T07:02:27+00:00

We want to clear any unused GPMC_CS_CONFIG7 register on restore to ensure unused chip selects are not enabled. Cc: Roger Quadros Signed-off-by: Tony Lindgren Link: https://lore.kernel.org/r/20210727101034.32148-1-tony@atomide.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: fix unused-function warning

2021-07-23T06:25:34+00:00

The tegra186_mc_client_sid_override() is only called from an #ifdef block: drivers/memory/tegra/tegra186.c:74:13: error: 'tegra186_mc_client_sid_override' defined but not used [-Werror=unused-function] 74 | static void tegra186_mc_client_sid_override(struct tegra_mc *mc, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Add another #ifdef around the called function. Fixes: 393d66fd2cac ("memory: tegra: Implement SID override programming") Signed-off-by: Arnd Bergmann Acked-by: Jon Hunter Link: https://lore.kernel.org/r/20210722090748.1157470-1-arnd@kernel.org Signed-off-by: Krzysztof Kozlowski

Merge tag 'memory-controller-drv-tegra-5.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

2021-06-17T00:36:30+00:00

Memory controller drivers for v5.14 - Tegra SoC, part two Second set of changes for Tegra SoC memory controller drivers, containing patchset from Thierry Reding: "The goal here is to avoid early identity mappings altogether and instead postpone the need for the identity mappings to when devices are attached to the SMMU. This works by making the SMMU driver coordinate with the memory controller driver on when to start enforcing SMMU translations. This makes Tegra behave in a more standard way and pushes the code to deal with the Tegra-specific programming into the NVIDIA SMMU implementation." This pulls a dependency from Will Deacon (ARM SMMU driver) and contains further ARM SMMU driver patches to resolve complex dependencies between different patchsets. The pull from Will contains only one patch ("Implement ->probe_finalize()"). Further work in Will's tree might depend on this patch, therefore patch was applied there. On the other hand, this ("Implement ->probe_finalize()") patch is also a dependency for ARM SMMU driver changes for Tegra. These changes, bringing seamless transition from the firmware framebuffer to the OS framebuffer, depend on earlier Tegra memory controller driver patches. * tag 'memory-controller-drv-tegra-5.14-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (37 commits) iommu/arm-smmu: Use Tegra implementation on Tegra186 iommu/arm-smmu: tegra: Implement SID override programming iommu/arm-smmu: tegra: Detect number of instances at runtime dt-bindings: arm-smmu: Add Tegra186 compatible string memory: tegra: Delete dead debugfs checking code iommu/arm-smmu: Implement ->probe_finalize() memory: tegra: Implement SID override programming memory: tegra: Split Tegra194 data into separate file memory: tegra: Add memory client IDs to tables memory: tegra: Unify drivers memory: tegra: Only initialize reset controller if available memory: tegra: Make IRQ support opitonal memory: tegra: Parameterize interrupt handler memory: tegra: Extract setup code into callback memory: tegra: Make per-SoC setup more generic memory: tegra: Push suspend/resume into SoC drivers memory: tegra: Introduce struct tegra_mc_ops memory: tegra: Unify struct tegra_mc across SoC generations memory: tegra: Consolidate register fields memory: tegra30-emc: Use devm_tegra_core_dev_init_opp_table() ... Link: https://lore.kernel.org/r/20210614195200.21657-1-krzysztof.kozlowski@canonical.com Signed-off-by: Olof Johansson

Merge tag 'memory-controller-drv-pl353-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

2021-06-12T15:53:06+00:00

Memory controller drivers for v5.14 - PL353 Bigger work around ARM Primecell PL35x SMC memory controller driver by Miquel Raynal built on previous series from Naga Sureshkumar Relli. This includes bindings cleanup and correction, converting these to dtschema and several cleanyps in pl353-smc driver. * tag 'memory-controller-drv-pl353-5.14' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: dt-binding: memory: pl353-smc: Convert to yaml MAINTAINERS: Add PL353 SMC entry memory: pl353-smc: Declare variables following a reverse christmas tree order memory: pl353-smc: Avoid useless acronyms in descriptions memory: pl353-smc: Let lower level controller drivers handle inits memory: pl353-smc: Rename goto labels memory: pl353-smc: Fix style dt-binding: memory: pl353-smc: Fix the NAND controller node in the example dt-binding: memory: pl353-smc: Drop unsupported nodes from the example dt-binding: memory: pl353-smc: Fix the example syntax and style dt-binding: memory: pl353-smc: Describe the child reg property dt-binding: memory: pl353-smc: Drop the partitioning section dt-binding: memory: pl353-smc: Document the range property dt-binding: memory: pl353-smc: Rephrase the binding Link: https://lore.kernel.org/r/20210611140659.61980-2-krzysztof.kozlowski@canonical.com Signed-off-by: Olof Johansson

memory: pl353-smc: Declare variables following a reverse christmas tree order

2021-06-10T15:15:16+00:00

This is a purely cosmetic change. Signed-off-by: Miquel Raynal Link: https://lore.kernel.org/r/20210610082040.2075611-15-miquel.raynal@bootlin.com Signed-off-by: Krzysztof Kozlowski