kernel/linux.git/drivers/memory/tegra, branch v4.18.2Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v4.18.22018-05-18T20:45:01+00:00memory: tegra: Remove Tegra114 SATA and AFI reset definitions2018-05-18T20:45:01+00:00Dmitry Osipenkodigetx@gmail.com2018-05-08T16:49:47+00:00urn:sha1:5fd80cf74e1ee06f9895b74d26a3efb01bdad033
Tegra114 doesn't have SATA nor PCIe, but TRM seems erroneously document
them.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Register SMMU after MC driver became ready2018-05-18T10:31:55+00:00Dmitry Osipenkodigetx@gmail.com2018-05-08T16:55:30+00:00urn:sha1:45a81df06eeb320093b06132870e7ecd646db3f0
Memory Controller driver invokes SMMU driver registration and MC's
registers mapping is shared with SMMU. This mapping goes away if MC
driver probing fails after SMMU registration.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra210 memory controller hot resets2018-04-30T08:12:21+00:00Thierry Redingtreding@nvidia.com2018-04-13T11:33:50+00:00urn:sha1:273d760060e365c37e6e5bb3c0810a5b93fa569d
Define the table of memory controller hot resets for Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra124 memory controller hot resets2018-04-30T08:12:21+00:00Dmitry Osipenkodigetx@gmail.com2018-04-13T11:33:51+00:00urn:sha1:1b19b0561d41966eb59c27157eab52be5bd97826
Define the table of memory controller hot resets for Tegra124.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra114 memory controller hot resets2018-04-30T08:12:21+00:00Dmitry Osipenkodigetx@gmail.com2018-04-13T11:33:52+00:00urn:sha1:3788c4ed4a38cb9329ac202fa1b77f738c1ae0a4
Define the table of memory controller hot resets for Tegra114.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra30 memory controller hot resets2018-04-30T08:12:21+00:00Dmitry Osipenkodigetx@gmail.com2018-04-13T11:33:53+00:00urn:sha1:ec4e1f0d66f53601011e4eb945d109bbae386fb5
Define the table of memory controller hot resets for Tegra30.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra20 memory controller hot resets2018-04-30T08:12:21+00:00Dmitry Osipenkodigetx@gmail.com2018-04-13T11:33:54+00:00urn:sha1:cb557757e1aace04fbfb94ab731c3cf7e33b95f8
Define the table of memory controller hot resets for Tegra20 and add
specific to Tegra20 hot reset operations.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Introduce memory client hot reset2018-04-30T08:12:21+00:00Dmitry Osipenkodigetx@gmail.com2018-04-13T11:33:49+00:00urn:sha1:20e92462cdfb2772e9d784ec355c90b61ec10222
In order to reset busy HW properly, memory controller needs to be
involved, otherwise it is possible to get corrupted memory or hang machine
if HW was reset during DMA. Introduce memory client 'hot reset' that will
be used for resetting of busy HW.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Squash tegra20-mc into common tegra-mc driver2018-04-30T08:10:00+00:00Dmitry Osipenkodigetx@gmail.com2018-04-09T19:28:31+00:00urn:sha1:a8d502fd33484ed8c4acc6acae73918844ca6811
Tegra30+ has some minor differences in registers / bits layout compared
to Tegra20. Let's squash Tegra20 driver into the common tegra-mc driver
in a preparation for the upcoming MC hot reset controls implementation,
avoiding code duplication.
Note that this currently doesn't report the value of MC_GART_ERROR_REQ
because it is located within the GART register area and cannot be safely
accessed from the MC driver (this happens to work only by accident). The
proper solution is to integrate the GART driver with the MC driver, much
like is done for the Tegra SMMU, but that is an invasive change and will
be part of a separate patch series.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Remove unused headers inclusions2018-04-27T09:23:52+00:00Dmitry Osipenkodigetx@gmail.com2018-04-09T19:28:30+00:00urn:sha1:85dce8918f90f71fc86ae822dd8cf4b738274f7e
Tegra210 contains some unused leftover headers, remove them for
consistency.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>