kernel/linux.git/drivers/memory/tegra/tegra30.c, branch v6.12.80

interconnect: constify of_phandle_args in xlate

2024-02-25T22:38:17+00:00

The xlate callbacks are supposed to translate of_phandle_args to proper provider without modifying the of_phandle_args. Make the argument pointer to const for code safety and readability. Acked-by: Konrad Dybcio Acked-by: Thierry Reding # Tegra Signed-off-by: Krzysztof Kozlowski Acked-by: Alim Akhtar # Samsung Link: https://lore.kernel.org/r/20240220072213.35779-1-krzysztof.kozlowski@linaro.org Signed-off-by: Georgi Djakov

memory: Explicitly include correct DT includes

2023-07-25T20:09:37+00:00

The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring Link: https://lore.kernel.org/r/20230714174717.4059518-1-robh@kernel.org Signed-off-by: Krzysztof Kozlowski

memory: tegra: Extract setup code into callback

2021-06-03T19:49:41+00:00

Separate the setup code for Tegra30 and later into a ->setup() callback and set it for all applicable chips. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-7-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Consolidate register fields

2021-06-03T19:49:40+00:00

Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra30: Support interconnect framework

2020-12-05T13:54:36+00:00

Now Internal and External memory controllers are memory interconnection providers. This allows us to use interconnect API for tuning of memory configuration. EMC driver now supports OPPs and DVFS. MC driver now supports tuning of memory arbitration latency, which needs to be done for ISO memory clients, like a Display client for example. Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Acked-by: Georgi Djakov Acked-by: Thierry Reding Link: https://lore.kernel.org/r/20201203192439.16177-4-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra30: Add FIFO sizes to memory clients

2020-11-26T17:50:36+00:00

The latency allowness is calculated based on buffering capabilities of memory clients. Add FIFO sizes to the Tegra30 memory clients. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201111011456.7875-7-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add missing latency allowness entry for Page Table Cache

2020-11-26T17:50:35+00:00

Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-32-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Consolidate registers definition into common header

2019-11-11T13:55:27+00:00

The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Signed-off-by: Thierry Reding

memory: tegra: Introduce Tegra30 EMC driver

2019-11-11T13:55:27+00:00

Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Signed-off-by: Thierry Reding

memory: tegra: Add gr2d and gr3d to DRM IOMMU group

2019-11-11T13:55:25+00:00

All of the devices making up the Tegra DRM device want to share a single IOMMU domain. Put them into a single group to allow them to do that. Signed-off-by: Thierry Reding