<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/memory/tegra/tegra234.c, branch linux-7.1.y</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=linux-7.1.y'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-03-07T17:02:41+00:00</updated>
<entry>
<title>memory: tegra: Prepare for supporting multiple intmask registers</title>
<updated>2026-03-07T17:02:41+00:00</updated>
<author>
<name>Ketan Patil</name>
<email>ketanp@nvidia.com</email>
</author>
<published>2026-02-26T16:31:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9f2614510960f0761144d14e1b4c4d82e0c098e9'/>
<id>urn:sha1:9f2614510960f0761144d14e1b4c4d82e0c098e9</id>
<content type='text'>
Add a new structure for the intmask register e.g. MC_INTMASK_0 and
it's mask value. Add an array of these new structures to prepare for
supporting multiple intmask registers. This is done in preparation for
adding support for Tegra264 which supports multiple intmask registers.

Signed-off-by: Ketan Patil &lt;ketanp@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Group SoC specific fields</title>
<updated>2026-03-07T17:02:29+00:00</updated>
<author>
<name>Ketan Patil</name>
<email>ketanp@nvidia.com</email>
</author>
<published>2026-02-26T16:31:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=2e4cfaa78eb98d2623367818c859225c6b6bf701'/>
<id>urn:sha1:2e4cfaa78eb98d2623367818c859225c6b6bf701</id>
<content type='text'>
Introduce new SoC specific fields in tegra_mc_soc struct for high
address mask and error status type mask because Tegra264 has different
values for these than the existing devices. Error status registers
e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the
error. In order to obtain such type of error from error status
register, we use error status type mask. Similarly, these error status
registers have bits which indicate the higher address bits of the
address responsible for mc error. In order to obtain such higher
address, we use high address mask. Make this change to prepare for
adding MC interrupt support for Tegra264.

Signed-off-by: Ketan Patil &lt;ketanp@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com
[krzk: Fix checkpatch warning]
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add support for multiple IRQs</title>
<updated>2026-03-07T16:59:37+00:00</updated>
<author>
<name>Ketan Patil</name>
<email>ketanp@nvidia.com</email>
</author>
<published>2026-02-26T16:31:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=4d865a2374037d2d0842f88822fd753f0918b370'/>
<id>urn:sha1:4d865a2374037d2d0842f88822fd753f0918b370</id>
<content type='text'>
Add support to handle multiple MC interrupts lines, as supported by
Tegra264. Turn the single IRQ handler callback into a counted array to
allow specifying a separate handler for each interrupt. Move IRQ
handlers into tegra_mc_soc struct, so as to specify SoC specific
values.

Signed-off-by: Ketan Patil &lt;ketanp@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Group error handling related registers</title>
<updated>2026-03-07T16:59:35+00:00</updated>
<author>
<name>Ketan Patil</name>
<email>ketanp@nvidia.com</email>
</author>
<published>2026-02-26T16:31:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=b8a177f18df1b439aac708da2d8bd9fcd68bb1eb'/>
<id>urn:sha1:b8a177f18df1b439aac708da2d8bd9fcd68bb1eb</id>
<content type='text'>
Group MC error related registers into a struct as they could have SoC
specific values. Tegra264 has different register offsets than the
existing devices and so in order to add support for Tegra264 we need to
first make this change.

Signed-off-by: Ketan Patil &lt;ketanp@nvidia.com&gt;
Reviewed-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Tested-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Fix indentation</title>
<updated>2024-02-22T08:48:53+00:00</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2024-02-20T12:44:30+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=ae1e06fb62c3a0fbcc7c58f45cf1a19641272799'/>
<id>urn:sha1:ae1e06fb62c3a0fbcc7c58f45cf1a19641272799</id>
<content type='text'>
Fix the indentation of the '.regs' member for the Tegra234 NVJPG memory
client.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://lore.kernel.org/r/20240220124430.19072-3-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add BPMP and ICC info for DLA clients</title>
<updated>2024-02-22T08:48:53+00:00</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2024-02-20T12:44:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=6a598c6c08dc6f34235ee6ee246962ccb14a47c3'/>
<id>urn:sha1:6a598c6c08dc6f34235ee6ee246962ccb14a47c3</id>
<content type='text'>
Add the BPMP IDs and ICC type information for the Tegra234 DLA memory
clients.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://lore.kernel.org/r/20240220124430.19072-2-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Correct DLA client names</title>
<updated>2024-02-22T08:48:52+00:00</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2024-02-20T12:44:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=51d915cbeef4c7a154f5d810b1e10d8125f2b0cc'/>
<id>urn:sha1:51d915cbeef4c7a154f5d810b1e10d8125f2b0cc</id>
<content type='text'>
Some of the names for the Tegra234 DLA clients are not unique and do not
align with the name of the client ID definitions. Therefore, it is not
possible to determine the exact DLA client from messages that print the
client name. Fix this by correcting the DLA memory client names for
Tegra234 to align with the name of the corresponding memory client ID.

Note that although the client names are also used by the interconnect
framework, interconnect support for the DLA clients has not been added
and so this issue does not impact the interconnect support.

Fixes: 5cd24ca0985f ("memory: tegra: Add DLA clients for Tegra234")
Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Link: https://lore.kernel.org/r/20240220124430.19072-1-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'memory-controller-drv-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into soc/drivers</title>
<updated>2023-10-16T21:00:46+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2023-10-16T21:00:46+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e855cbf28b6d46ac87dab630b1e56fd4a8fe9845'/>
<id>urn:sha1:e855cbf28b6d46ac87dab630b1e56fd4a8fe9845</id>
<content type='text'>
Memory controller drivers for v6.7

1. Atmel: Use __counted_by annotation.
2. Tegra: Add Tegra234 clients for RCE and VI.
3. Cleanup:
 - Use device_get_match_data() to simplify the code,
 - Make "additionalProperties: true" explicit in Devicetree bindings.

* tag 'memory-controller-drv-6.7' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: Use device_get_match_data()
  memory: tegra: Add Tegra234 clients for RCE and VI
  dt-bindings: memory-controllers: Make "additionalProperties: true" explicit
  memory: atmel-ebi: Annotate struct atmel_ebi_dev with __counted_by

Link: https://lore.kernel.org/r/20231016074013.28286-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Set BPMP msg flags to reset IPC channels</title>
<updated>2023-10-13T12:23:41+00:00</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2023-10-09T10:05:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=f344675a34383ae26a8230f4b1cd99cbd0defebd'/>
<id>urn:sha1:f344675a34383ae26a8230f4b1cd99cbd0defebd</id>
<content type='text'>
Set the 'TEGRA_BPMP_MESSAGE_RESET' bit in newly added 'flags' field
of 'struct tegra_bpmp_message' to request for the reset of BPMP IPC
channels. This is used along with the 'suspended' check in BPMP driver
for handling early bandwidth requests due to the hotplug of CPU's
during system resume before the driver gets resumed.

Fixes: f41e1442ac5b ("cpufreq: tegra194: add OPP support and set bandwidth")
Co-developed-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Signed-off-by: Sumit Gupta &lt;sumitg@nvidia.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Add Tegra234 clients for RCE and VI</title>
<updated>2023-10-12T13:30:25+00:00</updated>
<author>
<name>Jon Hunter</name>
<email>jonathanh@nvidia.com</email>
</author>
<published>2023-10-12T10:49:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9def28f3b8634e4f1fa92a77ccb65fbd2d03af34'/>
<id>urn:sha1:9def28f3b8634e4f1fa92a77ccb65fbd2d03af34</id>
<content type='text'>
Add the Tegra234 memory client entries for the Real-time Camera Engine
(RCE) and Video Input (VI) devices.

Signed-off-by: Jon Hunter &lt;jonathanh@nvidia.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20231012104909.48518-1-jonathanh@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
</feed>
