kernel/linux.git/drivers/memory/tegra/tegra210.c, branch v5.2.1Linux kernel stable tree (mirror)https://git.radix-linux.su/kernel/linux.git/atom?h=v5.2.12019-06-19T15:09:55+00:00treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 5002019-06-19T15:09:55+00:00Thomas Gleixnertglx@linutronix.de2019-06-04T08:11:33+00:00urn:sha1:d2912cb15bdda8ba4a5dd73396ad62641af2f520
Based on 2 normalized pattern(s):
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation
this program is free software you can redistribute it and or modify
it under the terms of the gnu general public license version 2 as
published by the free software foundation #
extracted by the scancode license scanner the SPDX license identifier
GPL-2.0-only
has been chosen to replace the boilerplate/reference in 4122 file(s).
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
memory: tegra: Properly spell "tegra"2019-04-11T15:58:41+00:00Thierry Redingtreding@nvidia.com2019-04-11T08:48:25+00:00urn:sha1:cb2b58391e40d0877b1f60023c8be72696ff8511
Rename all occurrences of "terga" to "tegra". It's an easy typo to make
and a difficult one to spot.
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra210 memory controller hot resets2018-04-30T08:12:21+00:00Thierry Redingtreding@nvidia.com2018-04-13T11:33:50+00:00urn:sha1:273d760060e365c37e6e5bb3c0810a5b93fa569d
Define the table of memory controller hot resets for Tegra210.
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Remove unused headers inclusions2018-04-27T09:23:52+00:00Dmitry Osipenkodigetx@gmail.com2018-04-09T19:28:30+00:00urn:sha1:85dce8918f90f71fc86ae822dd8cf4b738274f7e
Tegra210 contains some unused leftover headers, remove them for
consistency.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Apply interrupts mask per SoC2018-04-27T09:23:04+00:00Dmitry Osipenkodigetx@gmail.com2018-04-09T19:28:29+00:00urn:sha1:1c74d5c0de0c2cc29fef97a19251da2ad6f579bd
Currently we are enabling handling of interrupts specific to Tegra124+
which happen to overlap with previous generations. Let's specify
interrupts mask per SoC generation for consistency and in a preparation
of squashing of Tegra20 driver into the common one that will enable
handling of GART faults which may be undesirable by newer generations.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Create SMMU display groups2017-12-15T09:12:32+00:00Thierry Redingtreding@nvidia.com2017-10-12T14:29:19+00:00urn:sha1:2a8102dfe0da7dbb61794e6b85dc7ac9271e5fc8
Create SMMU display groups for Tegra30, Tegra114, Tegra124 and Tegra210.
This allows the display controllers on these devices to share the same
IOMMU domain using the standard IOMMU group mechanism.
Signed-off-by: Thierry Reding <treding@nvidia.com>
memory: tegra: Add Tegra210 support2015-08-13T14:07:52+00:00Thierry Redingtreding@nvidia.com2015-03-23T09:45:12+00:00urn:sha1:588c43a7bd5a53ae523b318e1db16bdd59963a3c
Add the table of memory clients and SWGROUPs for Tegra210 to enable SMMU
support for this new SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>