kernel/linux.git/drivers/memory/tegra/tegra114.c, branch v7.1

memory: tegra: Prepare for supporting multiple intmask registers

2026-03-07T17:02:41+00:00

Add a new structure for the intmask register e.g. MC_INTMASK_0 and it's mask value. Add an array of these new structures to prepare for supporting multiple intmask registers. This is done in preparation for adding support for Tegra264 which supports multiple intmask registers. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-6-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group SoC specific fields

2026-03-07T17:02:29+00:00

Introduce new SoC specific fields in tegra_mc_soc struct for high address mask and error status type mask because Tegra264 has different values for these than the existing devices. Error status registers e.g. MC_ERR_STATUS_0 has few bits which indicate the type of the error. In order to obtain such type of error from error status register, we use error status type mask. Similarly, these error status registers have bits which indicate the higher address bits of the address responsible for mc error. In order to obtain such higher address, we use high address mask. Make this change to prepare for adding MC interrupt support for Tegra264. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-5-ketanp@nvidia.com [krzk: Fix checkpatch warning] Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add support for multiple IRQs

2026-03-07T16:59:37+00:00

Add support to handle multiple MC interrupts lines, as supported by Tegra264. Turn the single IRQ handler callback into a counted array to allow specifying a separate handler for each interrupt. Move IRQ handlers into tegra_mc_soc struct, so as to specify SoC specific values. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-4-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Group error handling related registers

2026-03-07T16:59:35+00:00

Group MC error related registers into a struct as they could have SoC specific values. Tegra264 has different register offsets than the existing devices and so in order to add support for Tegra264 we need to first make this change. Signed-off-by: Ketan Patil Reviewed-by: Jon Hunter Tested-by: Jon Hunter Link: https://patch.msgid.link/20260226163115.1152181-2-ketanp@nvidia.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Extract setup code into callback

2021-06-03T19:49:41+00:00

Separate the setup code for Tegra30 and later into a ->setup() callback and set it for all applicable chips. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-7-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Consolidate register fields

2021-06-03T19:49:40+00:00

Subsequent patches will add more register fields to the tegra_mc_client structure, so consolidate all register field definitions into a common sub-structure for coherency. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add missing latency allowness entry for Page Table Cache

2020-11-26T17:50:35+00:00

Add missing PTC memory client latency allowness entry to the Tegra MC drivers. This prevents erroneous clearing of MC_INTSTATUS 0x0 register during of the LA programming in tegra_mc_setup_latency_allowance() due to the missing entry. Note that this patch doesn't fix any known problems. Signed-off-by: Dmitry Osipenko Link: https://lore.kernel.org/r/20201104164923.21238-32-digetx@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add gr2d and gr3d to DRM IOMMU group

2019-11-11T13:55:25+00:00

All of the devices making up the Tegra DRM device want to share a single IOMMU domain. Put them into a single group to allow them to do that. Signed-off-by: Thierry Reding

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500

2019-06-19T15:09:55+00:00

Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner Reviewed-by: Enrico Weigelt Reviewed-by: Kate Stewart Reviewed-by: Allison Randal Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman

memory: tegra: Fix a typos for "fdcdwr2" mc client

2019-04-18T09:51:17+00:00

Fix typo for fdcwr2 to fdcdwr2 to match the TRM. Signed-off-by: Edward Cragg Signed-off-by: Kejia Hu Acked-by: Jon Hunter Reviewed-by: Dmitry Osipenko Signed-off-by: Thierry Reding