kernel/linux.git/drivers/memory/tegra/Makefile, branch v6.19.11

memory: tegra: Add Tegra264 MC and EMC support

2025-07-11T14:49:42+00:00

Add support to enable Memory Controller (MC) and External Memory Controller (EMC) drivers for Tegra264. The nodes for MC and EMC are mostly the same as Tegra234 but differ in number of channels and interrupt numbers. The patch also adds the bandwidth manager definitions required for Tegra264 and uses them to populate the memory client table. All of these are needed to properly enable memory interconnect (ICC) support. Signed-off-by: Sumit Gupta Acked-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20250709222147.3758356-3-thierry.reding@gmail.com Signed-off-by: Thierry Reding

memory: tegra: Add Tegra234 support

2022-05-09T08:46:00+00:00

The memory controller and external memory controller found on Tegra234 is similar to the version found on earlier SoCs but supports a number of new memory clients. Add initial memory client definitions for the Tegra234 so that the SMMU stream ID override registers can be properly programmed at boot time. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20220506132312.3910637-2-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Split Tegra194 data into separate file

2021-06-03T19:49:41+00:00

Keep the directory structure consistent by splitting the Tegra194 data into a separate file. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-13-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Unify drivers

2021-06-03T19:49:41+00:00

The Tegra210 (and earlier) driver now supports all the functionality that the Tegra186 (and later) driver does, so they can be unified. Note that previously the Tegra186 (and later) driver could be unloaded, even if that was perhaps not very useful. Older chips don't support that yet, but once they do this code can be reenabled. Signed-off-by: Thierry Reding Link: https://lore.kernel.org/r/20210602163302.120041-11-thierry.reding@gmail.com Signed-off-by: Krzysztof Kozlowski

memory: tegra: Add EMC scaling sequence code for Tegra210

2020-06-22T11:54:57+00:00

This patch includes the sequence for clock tuning and the dynamic training mechanism for the clock above 800MHz. And historically there have been different sequences to change the EMC clock. The sequence to be used is specified in the EMC table. However, for the currently supported upstreaming platform, only the most recent sequence is used. So only support that in this patch. Based on the work of Peter De Schrijver . Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding

memory: tegra: Add EMC scaling support code for Tegra210

2020-06-22T11:54:57+00:00

This is the initial patch for Tegra210 EMC frequency scaling. It has the code to program various aspects of the EMC that are standardized, but it does not yet include the specific programming sequence needed for clock scaling. The driver is designed to support LPDDR4 SDRAM. Devices that use LPDDR4 need to perform training of the RAM before it can be used. Firmware will perform this training during early boot and pass a table of supported frequencies to the kernel via device tree. For the frequencies above 800 MHz, periodic retraining is needed to compensate for changes in timing. This periodic training will have to be performed until the frequency drops back to or below 800 MHz. This driver provides helpers used during this runtime retraining that will be used by the sequence specific code in a follow-up patch. Based on work by Peter De Schrijver . Signed-off-by: Joseph Lo Signed-off-by: Thierry Reding

memory: tegra: Add support for the Tegra194 memory controller

2020-01-09T18:38:38+00:00

The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding

memory: tegra: Support DVFS on Tegra186 and later

2020-01-09T18:35:54+00:00

Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding

memory: tegra: Introduce Tegra30 EMC driver

2019-11-11T13:55:27+00:00

Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver Signed-off-by: Dmitry Osipenko Tested-by: Peter Geis Signed-off-by: Thierry Reding

memory: tegra: Introduce Tegra20 EMC driver

2018-11-08T11:50:34+00:00

Introduce driver for the External Memory Controller (EMC) found on Tegra20 chips, which controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Signed-off-by: Dmitry Osipenko Acked-by: Peter De Schrijver Signed-off-by: Thierry Reding