<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/memory/tegra/Kconfig, branch v7.2-rc1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v7.2-rc1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2026-05-04T18:47:18+00:00</updated>
<entry>
<title>memory: tegra: Add Tegra114 EMC driver</title>
<updated>2026-05-04T18:47:18+00:00</updated>
<author>
<name>Svyatoslav Ryhel</name>
<email>clamor95@gmail.com</email>
</author>
<published>2026-04-27T07:03:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dce208b5405f40c36320bb0ee07e9df8f7f2bea4'/>
<id>urn:sha1:dce208b5405f40c36320bb0ee07e9df8f7f2bea4</id>
<content type='text'>
Introduce driver for the External Memory Controller (EMC) found in
Tegra114 SoC. It controls the external DRAM on the board. The purpose of
this driver is to program memory timing for external memory on the EMC
clock rate change.

Signed-off-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt;
Reviewed-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Link: https://patch.msgid.link/20260427070312.81679-5-clamor95@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Deduplicate rate request management code</title>
<updated>2026-05-04T17:16:48+00:00</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2026-05-01T07:00:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=8879cff7f86f82e8922208668fb0f7227e4836db'/>
<id>urn:sha1:8879cff7f86f82e8922208668fb0f7227e4836db</id>
<content type='text'>
As is, the EMC drivers for each 32-bit platform contain almost
identical duplicated code for aggregating rate requests. Move this
code out to a shared tegra-emc-common file to reduce duplication,
and add kerneldoc comments.

Based on code from the tegra20-emc driver.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Link: https://patch.msgid.link/20260501-memory-refactor-v3-1-69fb1ae1a7ca@nvidia.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Do not enable by default during compile testing</title>
<updated>2025-04-15T05:43:54+00:00</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2025-04-04T11:17:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=9a4199ae8a041bf75b544c1f46a2ea95417b69de'/>
<id>urn:sha1:9a4199ae8a041bf75b544c1f46a2ea95417b69de</id>
<content type='text'>
Enabling the compile test should not cause automatic enabling of all
drivers.

Link: https://lore.kernel.org/r/20250404111703.235455-2-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30-emc: Print additional memory info</title>
<updated>2022-01-27T09:40:34+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-12-22T04:32:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=e3aabb3c7dbe66201b45d7b2c20132196f491ad4'/>
<id>urn:sha1:e3aabb3c7dbe66201b45d7b2c20132196f491ad4</id>
<content type='text'>
Print out memory type and LPDDR2 configuration on Tegra30, making it
similar to the memory info printed by the Tegra20 memory driver. This
info is useful for debugging purposes.

Tested-by: Svyatoslav Ryhel &lt;clamor95@gmail.com&gt; # T30 ASUS TF201 LPDDR2
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20211222043215.28237-1-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra20-emc: Support matching timings by LPDDR2 configuration</title>
<updated>2021-10-15T07:52:47+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-10-06T22:46:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=131dd9a436d8f6dbaf3d9597803765d271b2fc19'/>
<id>urn:sha1:131dd9a436d8f6dbaf3d9597803765d271b2fc19</id>
<content type='text'>
ASUS Transformer TF101 doesn't provide RAM code and in this case memory
timings should be selected based on identity information read out from
SDRAM chip. Support matching timings by LPDDR2 configuration.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Enable compile testing for all drivers</title>
<updated>2021-06-03T12:24:03+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-06-01T02:31:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=56ebc9b0d77e0406aba2d900c82e79204cc7dc32'/>
<id>urn:sha1:56ebc9b0d77e0406aba2d900c82e79204cc7dc32</id>
<content type='text'>
Enable compile testing for all Tegra memory drivers.

Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra124: Support interconnect framework</title>
<updated>2021-01-05T17:03:22+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-28T15:49:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=380def2d4cf257663de42618e57134afeded32dd'/>
<id>urn:sha1:380def2d4cf257663de42618e57134afeded32dd</id>
<content type='text'>
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.

Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Acked-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201228154920.18846-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra124-emc: Make driver modular</title>
<updated>2021-01-05T17:00:09+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-28T15:49:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=281462e593483350d8072a118c6e072c550a80fa'/>
<id>urn:sha1:281462e593483350d8072a118c6e072c550a80fa</id>
<content type='text'>
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30: Support interconnect framework</title>
<updated>2020-12-05T13:54:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-03T19:24:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d76fa3f2c252421faf326afd5f445bed5d34075f'/>
<id>urn:sha1:d76fa3f2c252421faf326afd5f445bed5d34075f</id>
<content type='text'>
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory clients, like a Display client for example.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Acked-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20201203192439.16177-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30-emc: Make driver modular</title>
<updated>2020-11-26T17:50:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-11T01:14:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0c56eda86f8cad705d7d14e81e0e4efaeeaf4613'/>
<id>urn:sha1:0c56eda86f8cad705d7d14e81e0e4efaeeaf4613</id>
<content type='text'>
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201111011456.7875-8-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
</feed>
