<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/linux.git/drivers/memory/tegra/Kconfig, branch v5.16.1</title>
<subtitle>Linux kernel stable tree (mirror)</subtitle>
<id>https://git.radix-linux.su/kernel/linux.git/atom?h=v5.16.1</id>
<link rel='self' href='https://git.radix-linux.su/kernel/linux.git/atom?h=v5.16.1'/>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/'/>
<updated>2021-10-15T07:52:47+00:00</updated>
<entry>
<title>memory: tegra20-emc: Support matching timings by LPDDR2 configuration</title>
<updated>2021-10-15T07:52:47+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-10-06T22:46:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=131dd9a436d8f6dbaf3d9597803765d271b2fc19'/>
<id>urn:sha1:131dd9a436d8f6dbaf3d9597803765d271b2fc19</id>
<content type='text'>
ASUS Transformer TF101 doesn't provide RAM code and in this case memory
timings should be selected based on identity information read out from
SDRAM chip. Support matching timings by LPDDR2 configuration.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20211006224659.21434-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra: Enable compile testing for all drivers</title>
<updated>2021-06-03T12:24:03+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-06-01T02:31:13+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=56ebc9b0d77e0406aba2d900c82e79204cc7dc32'/>
<id>urn:sha1:56ebc9b0d77e0406aba2d900c82e79204cc7dc32</id>
<content type='text'>
Enable compile testing for all Tegra memory drivers.

Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>memory: tegra124: Support interconnect framework</title>
<updated>2021-01-05T17:03:22+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-28T15:49:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=380def2d4cf257663de42618e57134afeded32dd'/>
<id>urn:sha1:380def2d4cf257663de42618e57134afeded32dd</id>
<content type='text'>
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.

Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Acked-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201228154920.18846-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra124-emc: Make driver modular</title>
<updated>2021-01-05T17:00:09+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-28T15:49:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=281462e593483350d8072a118c6e072c550a80fa'/>
<id>urn:sha1:281462e593483350d8072a118c6e072c550a80fa</id>
<content type='text'>
Add modularization support to the Tegra124 EMC driver, which now can be
compiled as a loadable kernel module.

Note that EMC clock must be registered at clk-init time, otherwise PLLM
will be disabled as unused clock at boot time if EMC driver is compiled
as a module. Hence add a prepare/complete callbacks. similarly to what is
done for the Tegra20/30 EMC drivers.

Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201228154920.18846-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30: Support interconnect framework</title>
<updated>2020-12-05T13:54:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-12-03T19:24:32+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d76fa3f2c252421faf326afd5f445bed5d34075f'/>
<id>urn:sha1:d76fa3f2c252421faf326afd5f445bed5d34075f</id>
<content type='text'>
Now Internal and External memory controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS. MC driver now
supports tuning of memory arbitration latency, which needs to be done
for ISO memory clients, like a Display client for example.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Acked-by: Georgi Djakov &lt;georgi.djakov@linaro.org&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20201203192439.16177-4-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra30-emc: Make driver modular</title>
<updated>2020-11-26T17:50:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-11T01:14:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0c56eda86f8cad705d7d14e81e0e4efaeeaf4613'/>
<id>urn:sha1:0c56eda86f8cad705d7d14e81e0e4efaeeaf4613</id>
<content type='text'>
Add modularization support to the Tegra30 EMC driver, which now can be
compiled as a loadable kernel module.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201111011456.7875-8-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra20-emc: Add devfreq support</title>
<updated>2020-11-26T17:50:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-11T01:14:34+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=dedf62d6f17fc9cf0389602b6d3d7533cc218679'/>
<id>urn:sha1:dedf62d6f17fc9cf0389602b6d3d7533cc218679</id>
<content type='text'>
Add devfreq support to the Tegra20 EMC driver. Memory utilization
statistics will be periodically polled from the memory controller and
appropriate minimum clock rate will be selected by the devfreq governor.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Chanwoo Choi &lt;cw00.choi@samsung.com&gt;
Link: https://lore.kernel.org/r/20201111011456.7875-5-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra20: Support interconnect framework</title>
<updated>2020-11-26T17:50:36+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-04T16:49:11+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=d5ef16ba5fbe128873a55441d85ccde77f63c129'/>
<id>urn:sha1:d5ef16ba5fbe128873a55441d85ccde77f63c129</id>
<content type='text'>
Now Internal and External Memory Controllers are memory interconnection
providers. This allows us to use interconnect API for tuning of memory
configuration. EMC driver now supports OPPs and DVFS.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Link: https://lore.kernel.org/r/20201104164923.21238-36-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra20-emc: Make driver modular</title>
<updated>2020-11-26T17:50:35+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-04T16:49:09+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=0260979b018faaf90ff5a7bb04ac3f38e9dee6e3'/>
<id>urn:sha1:0260979b018faaf90ff5a7bb04ac3f38e9dee6e3</id>
<content type='text'>
Add modularization support to the Tegra20 EMC driver, which now can be
compiled as a loadable kernel module.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Link: https://lore.kernel.org/r/20201104164923.21238-34-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
<entry>
<title>memory: tegra-mc: Add interconnect framework</title>
<updated>2020-11-26T17:50:35+00:00</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-04T16:49:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.radix-linux.su/kernel/linux.git/commit/?id=06f079816d4c4e43d4128f394ae249934a32dffd'/>
<id>urn:sha1:06f079816d4c4e43d4128f394ae249934a32dffd</id>
<content type='text'>
Add common SoC-agnostic ICC framework which turns Tegra Memory Controller
into a memory interconnection provider. This allows us to use interconnect
API for tuning of memory configurations.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Tested-by: Peter Geis &lt;pgwipeout@gmail.com&gt;
Tested-by: Nicolas Chauvet &lt;kwizart@gmail.com&gt;
Link: https://lore.kernel.org/r/20201104164923.21238-33-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
</feed>
