memory: dfl-emif: Update the dfl emif driver support revision 1

2022-08-16T09:12:04+00:00

The next generation (revision 1) of the DFL EMIF feature device requires support for more than 4 memory banks. It does not support the selective clearing of memory banks. A capability register replaces the previous control register, and contains a bitmask to indicate the presence of each memory bank. This bitmask aligns with the previous control register bitmask that served the same purpose. The control and capability registers are treated like a C Union structure in order to support both the new and old revisions of the EMIF device. Signed-off-by: Debarati Biswas Signed-off-by: Russ Weight Signed-off-by: Tianfei Zhang Reviewed-by: Matthew Gerlach Signed-off-by: Krzysztof Kozlowski Link: https://lore.kernel.org/r/20220713130355.196115-1-tianfei.zhang@intel.com

memory: dfl-emif: add the DFL EMIF private feature driver

2021-01-07T14:21:27+00:00

This driver is for the EMIF private feature implemented under FPGA Device Feature List (DFL) framework. It is used to expose memory interface status information as well as memory clearing control. The purpose of memory clearing block is to zero out all private memory when FPGA is to be reprogrammed. This gives users a reliable method to prevent potential data leakage. [mdf@kernel.org: Fixed up ABI doc] Reviewed-by: Tom Rix Acked-by: Krzysztof Kozlowski Signed-off-by: Xu Yilun Signed-off-by: Russ Weight Link: https://lore.kernel.org/r/20210107043714.991646-9-mdf@kernel.org Signed-off-by: Greg Kroah-Hartman

kernel/linux.git/drivers/memory/dfl-emif.c, branch v6.18.21

memory: dfl-emif: Update the dfl emif driver support revision 1

memory: dfl-emif: add the DFL EMIF private feature driver