kernel/linux.git/drivers/mailbox, branch linux-6.0.y

mailbox: zynq-ipi: fix error handling while device_register() fails

2022-12-31T12:26:39+00:00

[ Upstream commit a6792a0cdef0b1c2d77920246283a72537e60e94 ] If device_register() fails, it has two issues: 1. The name allocated by dev_set_name() is leaked. 2. The parent of device is not NULL, device_unregister() is called in zynqmp_ipi_free_mboxes(), it will lead a kernel crash because of removing not added device. Call put_device() to give up the reference, so the name is freed in kobject_cleanup(). Add device registered check in zynqmp_ipi_free_mboxes() to avoid null-ptr-deref. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Yang Yingliang Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: arm_mhuv2: Fix return value check in mhuv2_probe()

2022-12-31T12:26:39+00:00

[ Upstream commit 165b7643f2df890066b1b4e8a387888a600ca9bf ] If devm_of_iomap() fails, it returns ERR_PTR() and never return NULL, so replace NULL pointer check with IS_ERR() to fix this problem. Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver") Signed-off-by: Yang Yingliang Acked-by: Viresh Kumar Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: mpfs: read the system controller's status

2022-12-31T12:26:39+00:00

[ Upstream commit ab47d0bfdf88faac0eb02749e5bfaa306e004300 ] Some services explicitly return an error code in their response, but others rely on the system controller to set a status in its status register. The meaning of the bits varies based on what service is requested, so pass it back up to the driver that requested the service in the first place. The field in the message struct already existed, but was unused until now. If the system controller is busy, in which case we should never actually be in the interrupt handler, or if the service fails the mailbox itself should not be read. Callers should check the status before operating on the response. There's an existing, but unused, #define for the mailbox mask - but it was incorrect. It was doing a GENMASK_ULL(32, 16) which should've just been a GENMASK(31, 16), so fix that up and start using it. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley Reviewed-by: Palmer Dabbelt Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: pcc: Reset pcc_chan_count to zero in case of PCC probe failure

2022-12-31T12:25:43+00:00

[ Upstream commit 6d7d3c287410c0ad499e478e2338dc3d7e3392b1 ] Currently, 'pcc_chan_count' is remains set to a non-zero value if PCC subspaces are parsed successfully but something else fail later during the initial PCC probing phase. This will result in pcc_mbox_request_channel trying to access the resources that are not initialised or allocated and may end up in a system crash. Reset pcc_chan_count to 0 when the PCC probe fails in order to prevent the possible issue as described above. Fixes: ce028702ddbc ("mailbox: pcc: Move bulk of PCCT parsing into pcc_mbox_probe") Signed-off-by: Huisong Li Reviewed-by: Sudeep Holla Signed-off-by: Rafael J. Wysocki Signed-off-by: Sasha Levin

mailbox: bcm-ferxrm-mailbox: Fix error check for dma_map_sg

2022-10-21T10:38:55+00:00

[ Upstream commit 6b207ce8a96a71e966831e3a13c38143ba9a73c1 ] dma_map_sg return 0 on error, fix the error check, and return -EIO to caller. Fixes: dbc049eee730 ("mailbox: Add driver for Broadcom FlexRM ring manager") Signed-off-by: Jack Wang Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: mpfs: account for mbox offsets while sending

2022-10-21T10:38:55+00:00

[ Upstream commit 0d1aadfe10ba17ebdeb96abb9638eb0f623f9b55 ] The mailbox offset is not only used for receiving messages, but it is also used by messages sent to the system controller by Linux that have a payload, such as the "digital signature service". It is also overloaded by certain other services (reprogramming of the FPGA fabric, see Link:) to have a meaning other than the offset the system controller should read from. When the driver was written, no such services of the latter type were in use & those of the former used an offset of zero so this has gone un-noticed. Link: https://www.microsemi.com/document-portal/doc_download/1245815-polarfire-fpga-and-polarfire-soc-fpga-system-services-user-guide # Section 5.2 Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: mpfs: fix handling of the reg property

2022-10-21T10:38:55+00:00

[ Upstream commit 2e10289d1f304f5082a4dda55a677b72b3bdb581 ] The "data" region of the PolarFire SoC's system controller mailbox is not one continuous register space - the system controller's QSPI sits between the control and data registers. Split the "data" reg into two parts: "data" & "control". Optionally get the "data" register address from the 3rd reg property in the devicetree & fall back to using the old base + MAILBOX_REG_OFFSET that the current code uses. Fixes: 83d7b1560810 ("mbox: add polarfire soc system controller mailbox") Signed-off-by: Conor Dooley Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

mailbox: imx: fix RST channel support

2022-10-21T10:38:55+00:00

[ Upstream commit 7e5cd064f73ccecd2ac1aadca078394bd25ea3ce ] Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated to include the CR register. Add the missed CR register to xcr array. Fixes: 82ab513baed5 ("mailbox: imx: support RST channel") Reported-by: Liu Ying Signed-off-by: Peng Fan Tested-by: Liu Ying # i.MX8qm/qxp MEK boards boot Signed-off-by: Jassi Brar Signed-off-by: Sasha Levin

Merge tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration

2022-08-08T17:19:40+00:00

Pull mailbox updates from Jassi Brar: - mtk: - use rx_callback instead of cmdq_task_cb - qcom: - add syscon const - add SM6375 compatible - imx: - enable RST channel - clear pending irqs * tag 'mailbox-v5.20' of git://git.linaro.org/landing-teams/working/fujitsu/integration: mailbox: imx: clear pending interrupts dt-bindings: mailbox: qcom-ipcc: Add SM6375 compatible mailbox: imx: support RST channel dt-bindings: mailbox: imx-mu: add RST channel dt-bindings: mailbox: qcom,apcs-kpss-global: Add syscon const for relevant entries mailbox: mtk-cmdq: Remove proprietary cmdq_task_cb

mailbox: imx: clear pending interrupts

2022-08-03T14:48:13+00:00

During MU initialization, there maybe pending GSR and RSR pending interrupt, clear them to avoid unexpected kernel dump when requesting mailbox channel Reviewed-by: Jacky Bai Reviewed-by: Ye Li Signed-off-by: Peng Fan Signed-off-by: Jassi Brar