Linux kernel stable tree (mirror) https://git.radix-linux.su/kernel/linux.git/atom?h=v6.18.21 2025-10-08T18:44:21+00:00 2025-10-08T18:44:21+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-10-08T18:44:21+00:00 urn:sha1:cd5a0afbdf8033dc83786315d63f8b325bdba2fd Pull mailbox updates from Jassi Brar: - Qualcomm: add Glymur CPUCP mailbox binding - Xilinx Zynq: misc cleanup - MediaTek: - add new GPUEB mailbox driver - cmdq: remove pm_runtime calls from send_data - gce: make clock-names optional - misc: - change mailbox-altera maintainer - remove redundant 'fast_io' in regmap_config - mhuv3: Remove no_free_ptr * tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: mtk-cmdq: Remove pm_runtime APIs from cmdq_mbox_send_data() mailbox: add MediaTek GPUEB IPI mailbox dt-bindings: mailbox: Add MT8196 GPUEB Mailbox mailbox: zynqmp-ipi: Fix SGI cleanup on unbind mailbox: zynqmp-ipi: Fix out-of-bounds access in mailbox cleanup loop mailbox: zynqmp-ipi: Remove dev.parent check in zynqmp_ipi_free_mboxes mailbox: zynqmp-ipi: Remove redundant mbox_controller_unregister() call mailbox: remove unneeded 'fast_io' parameter in regmap_config dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding MAINTAINERS: Change mailbox-altera maintainer mailbox: arm_mhuv3: Remove no_free_ptr() to maintain the original form of the pointer 2025-10-06T23:14:01+00:00 Nicolas Frattaroli nicolas.frattaroli@collabora.com 2025-10-03T20:15:06+00:00 urn:sha1:dbca0eabb821a6278925712a7bb263d0997e9c8f The MT8196 SoC uses an embedded MCU to control frequencies and power of the GPU. This controller is referred to as "GPUEB". It communicates to the application processor, among other ways, through a mailbox. The mailbox exposes one interrupt, which appears to only be fired when a response is received, rather than a transaction is completed. For us, this means we unfortunately need to poll for txdone. The mailbox also requires the EB clock to be on when touching any of the mailbox registers. Add a simple driver for it based on the common mailbox framework. Reviewed-by: Chia-I Wu <olvaffe@gmail.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Signed-off-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> 2025-09-25T01:32:00+00:00 Anup Patel apatel@ventanamicro.com 2025-08-18T04:09:03+00:00 urn:sha1:bf3022a4eb119c6b4e3424d6b19d8bfdfbc9bb57 Add a mailbox controller driver for the new SBI message proxy extension which is part of the SBI v3.0 specification. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Co-developed-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Rahul Pathak <rpathak@ventanamicro.com> Signed-off-by: Anup Patel <apatel@ventanamicro.com> Link: https://lore.kernel.org/r/20250818040920.272664-8-apatel@ventanamicro.com Signed-off-by: Paul Walmsley <pjw@kernel.org> 2025-08-06T17:45:05+00:00 Jammy Huang jammy_huang@aspeedtech.com 2025-07-22T01:31:17+00:00 urn:sha1:ae524eb766460a9f7957bf2db0968c9cccb71d90 Add mailbox controller driver for AST27XX SoCs, which provides independent tx/rx mailbox between different processors. There are 4 channels for each tx/rx mailbox and each channel has an 32-byte FIFO. Signed-off-by: Jammy Huang <jammy_huang@aspeedtech.com> Reviewed-by: Andrew Jeffery <andrew@codeconstruct.com.au> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> 2025-08-06T17:43:55+00:00 Justin Chen justin.chen@broadcom.com 2025-06-02T22:23:11+00:00 urn:sha1:52436007b862a90348ac8efc3a89eaceb2234f53 The bcm74110 mailbox driver is used to communicate with a co-processor for various power management and firmware related tasks. Signed-off-by: Justin Chen <justin.chen@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com> Tested-by: Florian Fainelli <florian.fainelli@broadcom.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> 2025-07-21T15:16:16+00:00 Arnd Bergmann arnd@arndb.de 2025-07-21T15:15:45+00:00 urn:sha1:c5b9bff35a9823c4dd803f0eda3b34be88bbcded Patches from Peter Chen <peter.chen@cixtech.com>: Cixtech P1 (internal name sky1) is high performance generic Armv9 SoC. Orion O6 is the Arm V9 Motherboard built by Radxa. You could find brief introduction for SoC and related boards at: https://radxa.com/products/orion/o6#overview Currently, to run upstream kernel at Orion O6 board, you need to use BIOS released by Radxa, and add "clk_ignore_unused=1" at bootargs. https://docs.radxa.com/en/orion/o6/bios/install-bios In this series, we add initial SoC and board support for Kernel building. Since mailbox is used for SCMI clock communication, mailbox driver is added in this series for the minimum SoC support. Patch 1-2: add dt-binding doc for CIX and its sky1 SoC Patch 3: add Arm64 build support Patch 4-5: add CIX mailbox driver which needs to support SCMI clock protocol. Patch 6: add Arm64 defconfig support Patch 7-8: add initial dts support for SoC and Orion O6 board Patch 9: add MAINTAINERS entry * newsoc/cix-p1: MAINTAINERS: Add CIX SoC maintainer entry arm64: dts: cix: Add sky1 base dts initial support dt-bindings: clock: cix: Add CIX sky1 scmi clock id arm64: defconfig: Enable CIX SoC mailbox: add CIX mailbox driver dt-bindings: mailbox: add cix,sky1-mbox arm64: Kconfig: add ARCH_CIX for cix silicons dt-bindings: arm: add CIX P1 (SKY1) SoC dt-bindings: vendor-prefixes: Add CIX Technology Group Co., Ltd. Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2025-07-21T15:14:55+00:00 Guomin Chen Guomin.Chen@cixtech.com 2025-07-21T14:44:56+00:00 urn:sha1:fe2aa2361ddba8f4ccf05123e0e14e9fb70ea701 The CIX mailbox controller, used in the Cix SoCs, like sky1. facilitates message transmission between multiple processors within the SoC, such as the AP, PM, audio DSP, SensorHub MCU, and others. Acked-by: Jassi Brar <jassisinghbrar@gmail.com> Reviewed-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Guomin Chen <Guomin.Chen@cixtech.com> Signed-off-by: Gary Yang <gary.yang@cixtech.com> Signed-off-by: Lihua Liu <Lihua.Liu@cixtech.com> Signed-off-by: Peter Chen <peter.chen@cixtech.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> 2025-05-26T21:23:39+00:00 Yuntao Dai d1581209858@live.com 2025-05-20T07:44:24+00:00 urn:sha1:529015a0e77a57e17801e4a3338d74674e1f5704 Add mailbox controller driver for CV18XX SoCs, which provides 8 channels and each channel has an 8-byte FIFO. Signed-off-by: Yuntao Dai <d1581209858@live.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> 2025-05-26T21:23:38+00:00 Yue Haibing yuehaibing@huawei.com 2025-04-11T07:57:47+00:00 urn:sha1:d635ba4207c31940398c41caa0cedd80f3b9c9c7 If COMPILE_TEST is y but RISCV_SBI is n, build fails: drivers/mailbox/mailbox-mchp-ipc-sbi.c: In function 'mchp_ipc_sbi_chan_send': drivers/mailbox/mailbox-mchp-ipc-sbi.c:119:23: error: storage size of 'ret' isn't known struct sbiret ret; ^~~ CC drivers/nvmem/lpc18xx_otp.o drivers/mailbox/mailbox-mchp-ipc-sbi.c:121:15: error: implicit declaration of function 'sbi_ecall' [-Werror=implicit-function-declaration] ret = sbi_ecall(SBI_EXT_MICROCHIP_TECHNOLOGY, command, channel, ^~~~~~~~~ move COMPILE_TEST to ARCH_MICROCHIP dependency as other drivers. Fixes: e4b1d67e7141 ("mailbox: add Microchip IPC support") Signed-off-by: Yue Haibing <yuehaibing@huawei.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com> 2025-01-18T22:18:48+00:00 Tudor Ambarus tudor.ambarus@linaro.org 2025-01-15T14:18:15+00:00 urn:sha1:fbf7e5ce408e0619072e84e93e875de52f2b5fa5 The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag bits for hardware interrupt generation and a shared register for passing mailbox messages. When the controller is used by the ACPM interface the shared register is ignored and the mailbox controller acts as a doorbell. The controller just raises the interrupt to APM after the ACPM interface has written the message to SRAM. Add support for the Samsung Exynos mailbox controller. Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>